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Rev | Author | Line No. | Line |
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687 | killagreg | 1 | #include <avr/io.h> |
2 | #include <avr/interrupt.h> |
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3 | |||
4 | |||
684 | killagreg | 5 | #include "main.h" |
6 | #include "uart1.h" |
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7 | #include "fifo.h" |
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8 | #include "ubx.h" |
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9 | |||
10 | |||
11 | |||
12 | // FIFO-objects and buffers for input and output |
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13 | |||
14 | //#define BUFSIZE_IN 0x96 |
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15 | //volatile uint8_t inbuf[BUFSIZE_IN]; |
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16 | //fifo_t infifo; |
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17 | |||
18 | #define BUFSIZE_OUT 0x96 |
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19 | volatile uint8_t outbuf[BUFSIZE_OUT]; |
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20 | fifo_t outfifo; |
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21 | |||
22 | /****************************************************************/ |
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23 | /* Initialization of the USART1 */ |
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24 | /****************************************************************/ |
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25 | void USART1_Init (void) |
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26 | { |
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27 | // USART1 Control and Status Register A, B, C and baud rate register |
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28 | uint8_t sreg = SREG; |
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29 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
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30 | |||
31 | // disable all interrupts before reconfiguration |
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32 | cli(); |
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33 | |||
34 | // disable RX-Interrupt |
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35 | UCSR1B &= ~(1 << RXCIE1); |
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36 | // disable TX-Interrupt |
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37 | UCSR1B &= ~(1 << TXCIE1); |
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38 | // disable DRE-Interrupt |
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702 | killagreg | 39 | UCSR1B &= ~(1 << UDRIE1); |
684 | killagreg | 40 | |
41 | // set direction of RXD1 and TXD1 pins |
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42 | // set RXD1 (PD2) as an input pin |
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702 | killagreg | 43 | PORTD |= (1 << PORTD2); |
701 | killagreg | 44 | DDRD &= ~(1 << DDD2); |
45 | |||
684 | killagreg | 46 | // set TXD1 (PD3) as an output pin |
702 | killagreg | 47 | PORTD |= (1 << PORTD3); |
701 | killagreg | 48 | DDRD |= (1 << DDD3); |
684 | killagreg | 49 | |
50 | // USART0 Baud Rate Register |
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51 | // set clock divider |
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52 | UBRR1H = (uint8_t)(ubrr>>8); |
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53 | UBRR1L = (uint8_t)ubrr; |
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54 | |||
55 | // enable double speed operation |
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56 | UCSR1A |= (1 << U2X1); |
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57 | // enable receiver and transmitter |
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58 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
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59 | // set asynchronous mode |
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60 | UCSR1C &= ~(1 << UMSEL11); |
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61 | UCSR1C &= ~(1 << UMSEL10); |
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62 | // no parity |
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63 | UCSR1C &= ~(1 << UPM11); |
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64 | UCSR1C &= ~(1 << UPM10); |
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65 | // 1 stop bit |
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66 | UCSR1C &= ~(1 << USBS1); |
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67 | // 8-bit |
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68 | UCSR1B &= ~(1 << UCSZ12); |
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69 | UCSR1C |= (1 << UCSZ11); |
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70 | UCSR1C |= (1 << UCSZ10); |
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71 | |||
72 | // flush receive buffer explicit |
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73 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
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74 | |||
75 | // enable interrupts at the end |
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76 | // enable RX-Interrupt |
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77 | UCSR1B |= (1 << RXCIE1); |
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78 | // enable TX-Interrupt |
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702 | killagreg | 79 | UCSR1B |= (1 << TXCIE1); |
684 | killagreg | 80 | // enable DRE interrupt |
81 | //UCSR1B |= (1 << UDRIE1); |
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82 | |||
83 | |||
84 | // restore global interrupt flags |
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85 | SREG = sreg; |
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86 | |||
87 | // inint FIFO buffer |
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88 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
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702 | killagreg | 89 | //fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
684 | killagreg | 90 | } |
91 | |||
702 | killagreg | 92 | /*int16_t USART1_putc (const uint8_t c) |
684 | killagreg | 93 | { |
94 | int16_t ret = fifo_put (&outfifo, c); |
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95 | // create an data register empty interrupt |
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96 | UCSR1B |= (1 << UDRIE1); |
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97 | |||
98 | return ret; |
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99 | } |
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702 | killagreg | 100 | */ |
684 | killagreg | 101 | /*int16_t USART1_getc_nowait () |
102 | { |
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103 | return fifo_get_nowait (&infifo); |
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104 | } |
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105 | |||
106 | |||
107 | uint8_t USART1_getc_wait () |
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108 | { |
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109 | return fifo_get_wait (&infifo); |
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110 | } |
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111 | */ |
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112 | |||
113 | /****************************************************************/ |
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114 | /* USART1 data register empty ISR */ |
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115 | /****************************************************************/ |
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702 | killagreg | 116 | /*ISR(USART1_UDRE_vect) |
684 | killagreg | 117 | { |
118 | // Move a character from the output buffer to the data register. |
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119 | // When the character was processed the next interrupt is generated. |
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120 | // If the output buffer is empty the DRE-interrupt is disabled. |
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121 | if (outfifo.count > 0) |
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122 | UDR1 = _inline_fifo_get (&outfifo); |
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123 | else |
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124 | UCSR1B &= ~(1 << UDRIE1); |
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125 | } |
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702 | killagreg | 126 | */ |
684 | killagreg | 127 | |
128 | /****************************************************************/ |
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129 | /* USART1 transmitter ISR */ |
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130 | /****************************************************************/ |
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702 | killagreg | 131 | /*ISR(USART1_TX_vect) |
684 | killagreg | 132 | { |
133 | |||
134 | } |
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702 | killagreg | 135 | */ |
684 | killagreg | 136 | /****************************************************************/ |
137 | /* USART1 receiver ISR */ |
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138 | /****************************************************************/ |
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139 | ISR(USART1_RX_vect) |
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140 | { |
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141 | uint8_t c; |
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702 | killagreg | 142 | c = UDR1; // get data byte |
757 | killagreg | 143 | if (BoardRelease == 11) ubx_parser(c); // and put it into the ubx protocol parser |
684 | killagreg | 144 | } |