Rev 687 | Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 684 | killagreg | 1 | #include "main.h" |
| 2 | #include "uart1.h" |
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| 3 | #include "fifo.h" |
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| 4 | #include "ubx.h" |
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| 5 | |||
| 6 | |||
| 7 | |||
| 8 | // FIFO-objects and buffers for input and output |
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| 9 | |||
| 10 | //#define BUFSIZE_IN 0x96 |
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| 11 | //volatile uint8_t inbuf[BUFSIZE_IN]; |
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| 12 | //fifo_t infifo; |
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| 13 | |||
| 14 | #define BUFSIZE_OUT 0x96 |
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| 15 | volatile uint8_t outbuf[BUFSIZE_OUT]; |
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| 16 | fifo_t outfifo; |
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| 17 | |||
| 18 | /****************************************************************/ |
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| 19 | /* Initialization of the USART1 */ |
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| 20 | /****************************************************************/ |
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| 21 | void USART1_Init (void) |
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| 22 | { |
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| 23 | // USART1 Control and Status Register A, B, C and baud rate register |
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| 24 | uint8_t sreg = SREG; |
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| 25 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
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| 26 | |||
| 27 | // disable all interrupts before reconfiguration |
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| 28 | cli(); |
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| 29 | |||
| 30 | // disable RX-Interrupt |
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| 31 | UCSR1B &= ~(1 << RXCIE1); |
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| 32 | // disable TX-Interrupt |
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| 33 | UCSR1B &= ~(1 << TXCIE1); |
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| 34 | // disable DRE-Interrupt |
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| 35 | UCSR1B |= (1 << UDRIE1); |
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| 36 | |||
| 37 | // disable receiver and transmitter (will flush the buffers) |
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| 38 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
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| 39 | |||
| 40 | // set direction of RXD1 and TXD1 pins |
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| 41 | // set RXD1 (PD2) as an input pin |
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| 42 | PORTD |= (1 << PORTD2); |
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| 43 | DDRD &= ~(1 << DDD2); |
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| 44 | // set TXD1 (PD3) as an output pin |
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| 45 | PORTD |= (1 << PORTD3); |
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| 46 | DDRD |= (1 << DDD3); |
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| 47 | |||
| 48 | // USART0 Baud Rate Register |
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| 49 | // set clock divider |
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| 50 | UBRR1H = (uint8_t)(ubrr>>8); |
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| 51 | UBRR1L = (uint8_t)ubrr; |
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| 52 | |||
| 53 | // enable double speed operation |
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| 54 | UCSR1A |= (1 << U2X1); |
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| 55 | // enable receiver and transmitter |
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| 56 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
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| 57 | // set asynchronous mode |
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| 58 | UCSR1C &= ~(1 << UMSEL11); |
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| 59 | UCSR1C &= ~(1 << UMSEL10); |
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| 60 | // no parity |
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| 61 | UCSR1C &= ~(1 << UPM11); |
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| 62 | UCSR1C &= ~(1 << UPM10); |
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| 63 | // 1 stop bit |
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| 64 | UCSR1C &= ~(1 << USBS1); |
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| 65 | // 8-bit |
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| 66 | UCSR1B &= ~(1 << UCSZ12); |
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| 67 | UCSR1C |= (1 << UCSZ11); |
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| 68 | UCSR1C |= (1 << UCSZ10); |
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| 69 | |||
| 70 | // flush receive buffer explicit |
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| 71 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
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| 72 | |||
| 73 | // enable interrupts at the end |
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| 74 | // enable RX-Interrupt |
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| 75 | UCSR1B |= (1 << RXCIE1); |
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| 76 | // enable TX-Interrupt |
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| 77 | //UCSR1B |= (1 << TXCIE1); |
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| 78 | // enable DRE interrupt |
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| 79 | //UCSR1B |= (1 << UDRIE1); |
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| 80 | |||
| 81 | |||
| 82 | // restore global interrupt flags |
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| 83 | SREG = sreg; |
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| 84 | |||
| 85 | // inint FIFO buffer |
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| 86 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
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| 87 | fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
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| 88 | } |
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| 89 | |||
| 90 | int16_t USART1_putc (const uint8_t c) |
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| 91 | { |
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| 92 | int16_t ret = fifo_put (&outfifo, c); |
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| 93 | // create an data register empty interrupt |
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| 94 | UCSR1B |= (1 << UDRIE1); |
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| 95 | |||
| 96 | return ret; |
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| 97 | } |
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| 98 | |||
| 99 | /*int16_t USART1_getc_nowait () |
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| 100 | { |
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| 101 | return fifo_get_nowait (&infifo); |
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| 102 | } |
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| 103 | |||
| 104 | |||
| 105 | uint8_t USART1_getc_wait () |
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| 106 | { |
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| 107 | return fifo_get_wait (&infifo); |
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| 108 | } |
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| 109 | */ |
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| 110 | |||
| 111 | /****************************************************************/ |
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| 112 | /* USART1 data register empty ISR */ |
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| 113 | /****************************************************************/ |
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| 114 | ISR(USART1_UDRE_vect) |
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| 115 | { |
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| 116 | // Move a character from the output buffer to the data register. |
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| 117 | // When the character was processed the next interrupt is generated. |
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| 118 | // If the output buffer is empty the DRE-interrupt is disabled. |
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| 119 | if (outfifo.count > 0) |
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| 120 | UDR1 = _inline_fifo_get (&outfifo); |
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| 121 | else |
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| 122 | UCSR1B &= ~(1 << UDRIE1); |
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| 123 | } |
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| 124 | |||
| 125 | /****************************************************************/ |
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| 126 | /* USART1 transmitter ISR */ |
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| 127 | /****************************************************************/ |
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| 128 | ISR(USART1_TX_vect) |
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| 129 | { |
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| 130 | |||
| 131 | } |
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| 132 | |||
| 133 | /****************************************************************/ |
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| 134 | /* USART1 receiver ISR */ |
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| 135 | /****************************************************************/ |
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| 136 | ISR(USART1_RX_vect) |
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| 137 | { |
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| 138 | uint8_t c; |
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| 139 | c = UDR0; // get data byte |
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| 140 | ubx_parser(c); // and put it into the ubx protocol parser |
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| 141 | } |