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| Rev | Author | Line No. | Line |
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| 1 | ingob | 1 | /*############################################################################ |
| 2 | ############################################################################*/ |
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| 3 | |||
| 4 | #ifndef BLMC_H_ |
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| 5 | #define BLMC_H_ |
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| 6 | |||
| 7 | extern volatile unsigned char Phase; |
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| 8 | extern volatile unsigned char ShadowTCCR1A; |
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| 9 | extern volatile unsigned char CompInterruptFreigabe; |
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| 10 | |||
| 11 | void Blc(void); |
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| 12 | void Manuell(void); |
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| 13 | |||
| 50 | holgerb | 14 | // anselm |
| 15 | /* |
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| 16 | #define COM1A ((0 << COM1A0) | (1 << COM1A1)) // COM1A-> OC1A non inverting mode |
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| 17 | #define COM1B ((0 << COM1B0) | (1 << COM1B1)) // COM1B-> OC1B non inverting mode |
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| 18 | #define COM2 ((0 << COM20) | (1 << COM21)) // COM2-> OC2 non inverting mode |
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| 19 | |||
| 20 | #ifdef _32KHZ |
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| 21 | #define WGM1 ((1 << WGM10) | (0 << WGM11)) // WGM10:13-> fast PWM 8bit |
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| 22 | #define WGMCS2 ((1 << WGM20) | (1 << WGM21) | (1 << CS20)) // WGM20:21-> fast PWM, no prescale |
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| 23 | #endif |
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| 24 | |||
| 25 | #ifdef _16KHZ |
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| 26 | #define WGM1 ((1 << WGM10) | (0 << WGM11)) // WGM10:13-> phase corr, PWM 8bit |
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| 27 | #define WGMCS2 ((1 << WGM20) | (0 << WGM21) | (1 << CS20)) // WGM20:21-> phase corr. PWM, no prescale |
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| 28 | #endif |
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| 29 | |||
| 30 | #define PWM_C_ON {TCCR1A = COM1A | WGM1 | COM1B; TCCR2 = WGMCS2; |
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| 31 | DDRB = 0x02;} // Steuer_C+ output |
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| 32 | #define PWM_B_ON {TCCR1A = COM1B | WGM1 | COM1A; TCCR2 = WGMCS2; \ |
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| 33 | DDRB = 0x04;} // Steuer_B+ output |
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| 34 | #define PWM_A_ON {TCCR1A = WGM1; TCCR2 = COM2 | WGMCS2; \ |
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| 35 | DDRB = 0x08;} // Steuer_A+ output |
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| 36 | #define PWM_OFF {TCCR1A = WGM1; \ |
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| 37 | TCCR2 = WGMCS2; \ |
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| 38 | PORTB &= ~0x0E; DDRB = 0x0E;} // OC1x & OC2 disconnected, Steuer_X+ output low |
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| 39 | // anselm |
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| 40 | */ |
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| 41 | |||
| 1 | ingob | 42 | #ifdef _32KHZ |
| 43 | #define PWM_C_ON {TCCR1A = 0xAD; TCCR2 = 0x49;DDRB = 0x0A;} |
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| 44 | #define PWM_B_ON {TCCR1A = 0xAD; TCCR2 = 0x49;DDRB = 0x0C;} |
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| 45 | #define PWM_A_ON {TCCR1A = 0xAD; TCCR2 = 0x69;DDRB = 0x08;} |
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| 46 | #define PWM_OFF {TCCR1A = 0x0D; TCCR2 = 0x49;PORTC &= ~0x0E;} |
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| 47 | #endif |
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| 48 | |||
| 49 | #ifdef _16KHZ |
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| 50 | holgerb | 50 | // #define PWM_C_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0A;} |
| 51 | // #define PWM_B_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0C;} |
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| 52 | // #define PWM_A_ON {TCCR1A = 0xA2; TCCR2 = 0x61; DDRB = 0x08;} |
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| 53 | |||
| 63 | hbuss | 54 | // #define PWM_C_ON {TCCR2 = 0x41; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x0A;} else { TCCR1A = 0x81; DDRB = 0x0E;}} |
| 55 | // #define PWM_B_ON {TCCR2 = 0x41; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x0C;} else { TCCR1A = 0x21; DDRB = 0x0E;}} |
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| 56 | // #define PWM_A_ON {TCCR2 = 0x61; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x08;} else { TCCR1A = 0x01; DDRB = 0x0E;}} |
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| 50 | holgerb | 57 | |
| 63 | hbuss | 58 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x02;} |
| 59 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x04;} |
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| 60 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x08;} |
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| 61 | |||
| 62 | |||
| 50 | holgerb | 63 | // #define PWM_C_ON {TCCR1A = 0x82; TCCR2 = 0x41; PORTB &= ~0x04; DDRB = 0x0E;} |
| 64 | // #define PWM_B_ON {TCCR1A = 0x22; TCCR2 = 0x41; PORTB &= ~0x02; DDRB = 0x0E;} |
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| 65 | // #define PWM_A_ON {TCCR1A = 0x02; TCCR2 = 0x61; PORTB &= ~0x06; DDRB = 0x0E;} |
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| 66 | |||
| 73 | hbuss | 67 | #define PWM_OFF {OCR1A = 0; OCR1B = 0; OCR2 = 0; TCCR1A = 0x01; TCCR2 = 0x41; DDRB = 0x0E; PORTB &= ~0x0E;} |
| 1 | ingob | 68 | #endif |
| 69 | |||
| 70 | #define STEUER_A_H {PWM_A_ON} |
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| 71 | #define STEUER_B_H {PWM_B_ON} |
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| 72 | #define STEUER_C_H {PWM_C_ON} |
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| 73 | |||
| 74 | #define STEUER_A_L {PORTD &= ~0x30; PORTD |= 0x08;} |
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| 75 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
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| 76 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
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| 50 | holgerb | 77 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF; } |
| 51 | holgerb | 78 | #define FETS_OFF {PORTD &= ~0x38; PORTB &= ~0x0E; } |
| 1 | ingob | 79 | |
| 73 | hbuss | 80 | #define SENSE_A ADMUX = 0 | IntRef; |
| 81 | #define SENSE_B ADMUX = 1 | IntRef; |
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| 82 | #define SENSE_C ADMUX = 2 | IntRef; |
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| 1 | ingob | 83 | |
| 84 | #define ClrSENSE ACSR |= 0x10 |
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| 85 | #define SENSE ((ACSR & 0x10)) |
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| 86 | #define SENSE_L (!(ACSR & 0x20)) |
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| 87 | #define SENSE_H ((ACSR & 0x20)) |
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| 88 | #define ENABLE_SENSE_INT {CompInterruptFreigabe = 1;ACSR |= 0x0A; } |
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| 89 | #define DISABLE_SENSE_INT {CompInterruptFreigabe = 0; ACSR &= ~0x08; } |
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| 90 | |||
| 91 | |||
| 92 | #define SENSE_FALLING_INT ACSR &= ~0x01 |
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| 93 | #define SENSE_RISING_INT ACSR |= 0x03 |
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| 94 | #define SENSE_TOGGLE_INT ACSR &= ~0x03 |
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| 95 | |||
| 96 | #endif //BLMC_H_ |
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| 97 |