Rev 426 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 426 | killagreg | 1 | |
| 2 | #include <stdlib.h> |
||
| 3 | #include <avr/io.h> |
||
| 4 | #include <avr/interrupt.h> |
||
| 5 | #include "analog.h" |
||
| 434 | killagreg | 6 | #include "printf_P.h" |
| 426 | killagreg | 7 | |
| 8 | volatile uint16_t Adc0, Adc1, Adc2, Adc3, Adc4, Adc5, Adc6, Adc7; |
||
| 9 | volatile uint8_t ADReady = 1; |
||
| 10 | |||
| 11 | /*****************************************************/ |
||
| 12 | /* Initialize Analog Digital Converter */ |
||
| 13 | /*****************************************************/ |
||
| 14 | void ADC_Init(void) |
||
| 15 | { |
||
| 16 | uint8_t sreg = SREG; |
||
| 434 | killagreg | 17 | printf("\r\n ADC init..."); |
| 426 | killagreg | 18 | // disable all interrupts before reconfiguration |
| 19 | cli(); |
||
| 20 | //ADC0 ... ADC7 is connected to PortA pin 0 ... 7 |
||
| 21 | DDRA = 0x00; |
||
| 22 | PORTA = 0x00; |
||
| 23 | // Digital Input Disable Register 0 |
||
| 24 | // Disable digital input buffer for analog adc_channel pins |
||
| 25 | DIDR0 = 0xFF; |
||
| 26 | // external reference AREF, adjust data to the right |
||
| 27 | ADMUX &= ~((1 << REFS1)|(1 << REFS0)|(1 << ADLAR)); |
||
| 28 | // set muxer to ADC adc_channel 0 (0 to 7 is a valid choice) |
||
| 29 | ADMUX = (ADMUX & 0xE0) | 0x00; |
||
| 30 | //Set ADC Control and Status Register A |
||
| 31 | //Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz |
||
| 32 | ADCSRA = (0<<ADEN)|(0<<ADSC)|(0<<ADATE)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)|(0<<ADIE); |
||
| 33 | //Set ADC Control and Status Register B |
||
| 34 | //Trigger Source to Free Running Mode |
||
| 35 | ADCSRB &= ~((1 << ADTS2)|(1 << ADTS1)|(1 << ADTS0)); |
||
| 36 | // Start AD conversion |
||
| 37 | ADC_Enable(); |
||
| 38 | // restore global interrupt flags |
||
| 39 | SREG = sreg; |
||
| 434 | killagreg | 40 | sei(); |
| 41 | printf("ok"); |
||
| 426 | killagreg | 42 | } |
| 43 | |||
| 44 | /*****************************************************/ |
||
| 45 | /* Interrupt Service Routine for ADC */ |
||
| 46 | /*****************************************************/ |
||
| 47 | // runs at 312.5 kHz or 3.2 µs |
||
| 48 | // if after (60.8µs) all 19 states are processed the interrupt is disabled |
||
| 49 | // and the update of further ads is stopped |
||
| 50 | |||
| 51 | |||
| 52 | #define ADC0 0 |
||
| 53 | #define ADC1 1 |
||
| 54 | #define ADC2 2 |
||
| 55 | #define ADC3 3 |
||
| 56 | #define ADC4 4 |
||
| 57 | #define ADC5 5 |
||
| 58 | #define ADC6 6 |
||
| 59 | #define ADC7 7 |
||
| 60 | |||
| 61 | ISR(ADC_vect) |
||
| 62 | { |
||
| 63 | static uint8_t ad_channel = ADC0, state = 0; |
||
| 64 | |||
| 65 | // state machine |
||
| 66 | switch(state++) |
||
| 67 | { |
||
| 68 | case 0: |
||
| 69 | Adc0 = ADC; |
||
| 70 | ad_channel = ADC1; |
||
| 71 | break; |
||
| 72 | case 1: |
||
| 73 | Adc1 = ADC; |
||
| 74 | ad_channel = ADC2; |
||
| 75 | break; |
||
| 76 | case 2: |
||
| 77 | Adc2 = ADC; |
||
| 78 | ad_channel = ADC3; |
||
| 79 | break; |
||
| 80 | case 3: |
||
| 81 | Adc3 = ADC; |
||
| 82 | ad_channel = ADC4; |
||
| 83 | break; |
||
| 84 | case 4: |
||
| 85 | Adc4 = ADC; |
||
| 86 | ad_channel = ADC5; |
||
| 87 | break; |
||
| 88 | case 5: |
||
| 89 | Adc5 = ADC; |
||
| 90 | ad_channel = ADC6; |
||
| 91 | break; |
||
| 92 | case 6: |
||
| 93 | Adc6 = ADC; |
||
| 94 | ad_channel = ADC7; |
||
| 95 | break; |
||
| 96 | case 7: |
||
| 97 | Adc7 = ADC; |
||
| 98 | ad_channel = ADC0; |
||
| 99 | state = 0; |
||
| 100 | ADReady = 1; |
||
| 101 | break; |
||
| 102 | default: |
||
| 103 | ad_channel = ADC0; |
||
| 104 | state = 0; |
||
| 105 | ADReady = 1; |
||
| 106 | break; |
||
| 107 | } |
||
| 108 | // set adc muxer to next ad_channel |
||
| 109 | ADMUX = (ADMUX & 0xE0) | ad_channel; |
||
| 110 | // after full cycle stop further interrupts |
||
| 111 | if(state != 0) ADC_Enable(); |
||
| 112 | } |