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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 428 | killagreg | 1 | |
| 2 | #include <stdlib.h> |
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| 3 | #include <avr/io.h> |
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| 4 | #include <avr/interrupt.h> |
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| 5 | |||
| 6 | #include "analog.h" |
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| 7 | |||
| 8 | volatile uint16_t Adc0, Adc1, Adc2, Adc3, Adc4, Adc5, Adc6, Adc7; |
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| 9 | volatile uint8_t ADReady = 1; |
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| 10 | |||
| 11 | /*****************************************************/ |
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| 12 | /* Initialize Analog Digital Converter */ |
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| 13 | /*****************************************************/ |
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| 14 | void ADC_Init(void) |
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| 15 | { |
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| 16 | uint8_t sreg = SREG; |
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| 17 | // disable all interrupts before reconfiguration |
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| 18 | cli(); |
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| 19 | //ADC0 ... ADC7 is connected to PortA pin 0 ... 7 |
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| 20 | DDRA = 0x00; |
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| 21 | PORTA = 0x00; |
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| 22 | // Digital Input Disable Register 0 |
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| 23 | // Disable digital input buffer for analog adc_channel pins |
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| 24 | DIDR0 = 0xFF; |
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| 25 | // external reference AREF, adjust data to the right |
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| 26 | ADMUX &= ~((1 << REFS1)|(1 << REFS0)|(1 << ADLAR)); |
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| 27 | // set muxer to ADC adc_channel 0 (0 to 7 is a valid choice) |
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| 28 | ADMUX = (ADMUX & 0xE0) | 0x00; |
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| 29 | //Set ADC Control and Status Register A |
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| 30 | //Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz |
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| 31 | ADCSRA = (0<<ADEN)|(0<<ADSC)|(0<<ADATE)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)|(0<<ADIE); |
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| 32 | //Set ADC Control and Status Register B |
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| 33 | //Trigger Source to Free Running Mode |
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| 34 | ADCSRB &= ~((1 << ADTS2)|(1 << ADTS1)|(1 << ADTS0)); |
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| 35 | // Start AD conversion |
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| 36 | ADC_Enable(); |
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| 37 | // restore global interrupt flags |
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| 38 | SREG = sreg; |
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| 39 | } |
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| 40 | |||
| 41 | /*****************************************************/ |
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| 42 | /* Interrupt Service Routine for ADC */ |
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| 43 | /*****************************************************/ |
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| 44 | // runs at 312.5 kHz or 3.2 µs |
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| 45 | // if after (60.8µs) all 19 states are processed the interrupt is disabled |
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| 46 | // and the update of further ads is stopped |
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| 47 | |||
| 48 | |||
| 49 | #define ADC0 0 |
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| 50 | #define ADC1 1 |
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| 51 | #define ADC2 2 |
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| 52 | #define ADC3 3 |
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| 53 | #define ADC4 4 |
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| 54 | #define ADC5 5 |
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| 55 | #define ADC6 6 |
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| 56 | #define ADC7 7 |
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| 57 | |||
| 58 | ISR(ADC_vect) |
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| 59 | { |
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| 60 | static uint8_t ad_channel = ADC0, state = 0; |
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| 61 | |||
| 62 | // state machine |
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| 63 | switch(state++) |
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| 64 | { |
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| 65 | case 0: |
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| 66 | Adc0 = ADC; |
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| 67 | ad_channel = ADC1; |
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| 68 | break; |
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| 69 | case 1: |
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| 70 | Adc1 = ADC; |
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| 71 | ad_channel = ADC2; |
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| 72 | break; |
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| 73 | case 2: |
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| 74 | Adc2 = ADC; |
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| 75 | ad_channel = ADC3; |
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| 76 | break; |
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| 77 | case 3: |
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| 78 | Adc3 = ADC; |
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| 79 | ad_channel = ADC4; |
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| 80 | break; |
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| 81 | case 4: |
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| 82 | Adc4 = ADC; |
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| 83 | ad_channel = ADC5; |
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| 84 | break; |
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| 85 | case 5: |
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| 86 | Adc5 = ADC; |
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| 87 | ad_channel = ADC6; |
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| 88 | break; |
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| 89 | case 6: |
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| 90 | Adc6 = ADC; |
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| 91 | ad_channel = ADC7; |
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| 92 | break; |
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| 93 | case 7: |
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| 94 | Adc7 = ADC; |
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| 95 | ad_channel = ADC0; |
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| 96 | state = 0; |
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| 97 | ADReady = 1; |
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| 98 | break; |
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| 99 | default: |
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| 100 | ad_channel = ADC0; |
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| 101 | state = 0; |
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| 102 | ADReady = 1; |
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| 103 | break; |
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| 104 | } |
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| 105 | // set adc muxer to next ad_channel |
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| 106 | ADMUX = (ADMUX & 0xE0) | ad_channel; |
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| 107 | // after full cycle stop further interrupts |
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| 108 | if(state != 0) ADC_Enable(); |
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| 109 | } |