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| Rev | Author | Line No. | Line |
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| 471 | cascade | 1 | /**************************************************************************** |
| 2 | * Copyright (C) 2009 by Claas Anders "CaScAdE" Rathje * |
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| 3 | * admiralcascade@gmail.com * |
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| 4 | * Project-URL: http://www.mylifesucks.de/oss/c-osd/ * |
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| 5 | * * |
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| 6 | * This program is free software; you can redistribute it and/or modify * |
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| 7 | * it under the terms of the GNU General Public License as published by * |
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| 8 | * the Free Software Foundation; either version 2 of the License. * |
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| 9 | * * |
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| 10 | * This program is distributed in the hope that it will be useful, * |
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| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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| 13 | * GNU General Public License for more details. * |
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| 14 | * * |
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| 15 | * You should have received a copy of the GNU General Public License * |
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| 16 | * along with this program; if not, write to the * |
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| 17 | * Free Software Foundation, Inc., * |
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| 18 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * |
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| 19 | ****************************************************************************/ |
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| 20 | |||
| 21 | #include <avr/io.h> |
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| 22 | #include <avr/interrupt.h> |
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| 23 | #include "spi.h" |
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| 24 | #include "main.h" |
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| 25 | |||
| 514 | cascade | 26 | #if !(ALLCHARSDEBUG|(WRITECHARS != -1)) |
| 27 | |||
| 471 | cascade | 28 | volatile uint16_t icnt = 0; |
| 507 | cascade | 29 | volatile uint8_t request_count = 0; |
| 471 | cascade | 30 | volatile uint8_t spi_ready = 1; |
| 507 | cascade | 31 | volatile union SPI_buffer_t SPI_buffer; |
| 32 | int16_t ampere = 0, max_ampere = 0, s_volt; |
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| 471 | cascade | 33 | int32_t ampere_wasted = 0; |
| 34 | |||
| 35 | #define INT0_HIGH PORTD |= (1 << PD2); |
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| 36 | #define INT0_LOW PORTD &= ~(1 << PD2); |
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| 37 | |||
| 38 | /** |
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| 39 | * init the SPI as master |
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| 40 | */ |
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| 41 | void SpiMasterInit(void) { |
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| 42 | volatile char IOReg; |
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| 43 | // set PB4(/SS), PB5(MOSI), PB7(SCK) as output |
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| 44 | DDRB = (1 << PB4) | (1 << PB5) | (1 << PB7); |
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| 45 | PORTB |= (1 << PB4); // pullup SS |
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| 46 | // enable SPI Interrupt and SPI in Master Mode with SCK = CK/128 |
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| 47 | SPCR = (1 << SPIE) | (1 << SPE) | (1 << MSTR) | (1 << SPR0) | (1 << SPR1); |
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| 48 | IOReg = SPSR; // clear SPIF bit in SPSR |
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| 49 | IOReg = SPDR; |
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| 50 | //sei(); // we do it later |
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| 51 | } |
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| 52 | |||
| 53 | |||
| 54 | /** |
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| 55 | * SPI interrupt handler |
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| 56 | */ |
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| 57 | ISR(SPI_STC_vect) { |
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| 507 | cascade | 58 | if (request_count == 0) { |
| 59 | SPI_buffer.buffer.chk = SPDR; // firs char received is check byte from last transfer |
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| 60 | } else { |
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| 61 | SPI_buffer.buffer.c[request_count - 1] = SPDR; // safe received byte to buffer |
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| 62 | } |
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| 63 | request_count++; |
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| 64 | if (--icnt) { |
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| 471 | cascade | 65 | //SPDR = *iptr; // send next byte |
| 66 | spi_ready = 1; // we _should_ send later because the slave needs more time |
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| 67 | } else { |
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| 68 | SPCR &= ~_BV(SPIE); // deactivate interrupt |
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| 69 | INT0_HIGH // transfer is done, slave does not need to listen |
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| 70 | } |
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| 71 | } |
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| 72 | |||
| 73 | /** |
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| 74 | * check if SPI transfer is still busy |
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| 75 | */ |
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| 76 | int TransferIsBusy(void) { |
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| 77 | return SPCR & _BV(SPIE); |
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| 78 | } |
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| 79 | |||
| 80 | /** |
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| 507 | cascade | 81 | * start a new transfer with length <len> |
| 471 | cascade | 82 | */ |
| 507 | cascade | 83 | void StartTransfer(uint16_t len) { |
| 471 | cascade | 84 | INT0_LOW // /SS LOW ^= SS HIGH ^= slave should listen |
| 85 | |||
| 507 | cascade | 86 | // this is a new request |
| 87 | request_count = 0; |
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| 88 | |||
| 471 | cascade | 89 | // set up pointer and length for interrupt handler |
| 90 | icnt = len; |
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| 91 | |||
| 92 | SPCR |= _BV(SPIE); // enable spi interrupt |
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| 507 | cascade | 93 | SPDR = 'A'; // start transfer by first command char |
| 471 | cascade | 94 | } |
| 507 | cascade | 95 | |
| 96 | /** |
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| 97 | * send next command through spi |
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| 98 | */ |
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| 99 | void spi_send_next() { |
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| 100 | SPDR = 'A' + request_count; |
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| 101 | } |
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| 514 | cascade | 102 | |
| 103 | #endif |