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471 | cascade | 1 | /**************************************************************************** |
2 | * Copyright (C) 2009 by Claas Anders "CaScAdE" Rathje * |
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3 | * admiralcascade@gmail.com * |
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4 | * Project-URL: http://www.mylifesucks.de/oss/c-osd/ * |
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5 | * * |
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6 | * This program is free software; you can redistribute it and/or modify * |
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7 | * it under the terms of the GNU General Public License as published by * |
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8 | * the Free Software Foundation; either version 2 of the License. * |
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9 | * * |
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10 | * This program is distributed in the hope that it will be useful, * |
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11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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13 | * GNU General Public License for more details. * |
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14 | * * |
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15 | * You should have received a copy of the GNU General Public License * |
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16 | * along with this program; if not, write to the * |
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17 | * Free Software Foundation, Inc., * |
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18 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * |
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19 | ****************************************************************************/ |
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20 | |||
21 | #include <avr/io.h> |
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22 | #include <avr/interrupt.h> |
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23 | #include "spi.h" |
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24 | #include "main.h" |
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25 | |||
26 | volatile uint16_t icnt = 0; |
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27 | volatile unsigned char * iptr; |
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28 | volatile unsigned char spi_cmd_buffer[8]; |
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29 | volatile uint8_t spi_ready = 1; |
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30 | int16_t ampere = 0, max_ampere = 0; |
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31 | int32_t ampere_wasted = 0; |
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32 | |||
33 | #define INT0_HIGH PORTD |= (1 << PD2); |
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34 | #define INT0_LOW PORTD &= ~(1 << PD2); |
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35 | |||
36 | /** |
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37 | * init the SPI as master |
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38 | */ |
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39 | void SpiMasterInit(void) { |
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40 | volatile char IOReg; |
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41 | // set PB4(/SS), PB5(MOSI), PB7(SCK) as output |
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42 | DDRB = (1 << PB4) | (1 << PB5) | (1 << PB7); |
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43 | PORTB |= (1 << PB4); // pullup SS |
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44 | // enable SPI Interrupt and SPI in Master Mode with SCK = CK/128 |
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45 | SPCR = (1 << SPIE) | (1 << SPE) | (1 << MSTR) | (1 << SPR0) | (1 << SPR1); |
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46 | IOReg = SPSR; // clear SPIF bit in SPSR |
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47 | IOReg = SPDR; |
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48 | //sei(); // we do it later |
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49 | } |
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50 | |||
51 | |||
52 | /** |
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53 | * SPI interrupt handler |
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54 | */ |
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55 | ISR(SPI_STC_vect) { |
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56 | *iptr++ = SPDR; // safe received byte to buffer |
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57 | icnt--; // dec length |
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58 | if (icnt) { |
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59 | //SPDR = *iptr; // send next byte |
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60 | spi_ready = 1; // we _should_ send later because the slave needs more time |
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61 | } else { |
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62 | SPCR &= ~_BV(SPIE); // deactivate interrupt |
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63 | INT0_HIGH // transfer is done, slave does not need to listen |
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64 | } |
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65 | } |
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66 | |||
67 | /** |
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68 | * check if SPI transfer is still busy |
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69 | */ |
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70 | int TransferIsBusy(void) { |
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71 | return SPCR & _BV(SPIE); |
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72 | } |
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73 | |||
74 | /** |
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75 | * start a new transfer of <data> with length <len> |
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76 | */ |
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77 | void StartTransfer(unsigned char *data, uint16_t len) { |
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78 | INT0_LOW // /SS LOW ^= SS HIGH ^= slave should listen |
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79 | |||
80 | // set up pointer and length for interrupt handler |
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81 | iptr = data; |
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82 | icnt = len; |
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83 | |||
84 | SPCR |= _BV(SPIE); // enable spi interrupt |
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85 | SPDR = *iptr; // start transfer by first bye |
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86 | } |