Details | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1702 | - | 1 | /* Copyright 2009-2011 Oleg Mazurov, Circuits At Home, http://www.circuitsathome.com */ |
2 | /* MAX3421E register/bit names and bitmasks */ |
||
3 | |||
4 | #ifndef _MAX3421Econstants_h_ |
||
5 | #define _MAX3421Econstants_h_ |
||
6 | |||
7 | /* SPI pins for diffrent Arduinos */ |
||
8 | |||
9 | #if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__) |
||
10 | #define SCK_PIN 52 |
||
11 | #define MISO_PIN 50 |
||
12 | #define MOSI_PIN 51 |
||
13 | #define SS_PIN 53 |
||
14 | #endif |
||
15 | #if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__) |
||
16 | #define SCK_PIN 13 |
||
17 | #define MISO_PIN 12 |
||
18 | #define MOSI_PIN 11 |
||
19 | #define SS_PIN 10 |
||
20 | #endif |
||
21 | |||
22 | #define MAX_SS 10 |
||
23 | #define MAX_INT 9 |
||
24 | #define MAX_GPX 8 |
||
25 | #define MAX_RESET 7 |
||
26 | |||
27 | /* "Breakpoint" pins for debugging */ |
||
28 | //#define BPNT_0 3 |
||
29 | //#define BPNT_1 2 |
||
30 | |||
31 | //#define Select_MAX3421E digitalWrite(MAX_SS,LOW) |
||
32 | //#define Deselect_MAX3421E digitalWrite(MAX_SS,HIGH) |
||
33 | |||
34 | /* */ |
||
35 | |||
36 | #define ON true |
||
37 | #define OFF false |
||
38 | |||
39 | /* VBUS states */ |
||
40 | #define SE0 0 |
||
41 | #define SE1 1 |
||
42 | #define FSHOST 2 |
||
43 | #define LSHOST 3 |
||
44 | |||
45 | /* MAX3421E command byte format: rrrrr0wa where 'r' is register number */ |
||
46 | // |
||
47 | // MAX3421E Registers in HOST mode. |
||
48 | // |
||
49 | #define rRCVFIFO 0x08 //1<<3 |
||
50 | #define rSNDFIFO 0x10 //2<<3 |
||
51 | #define rSUDFIFO 0x20 //4<<3 |
||
52 | #define rRCVBC 0x30 //6<<3 |
||
53 | #define rSNDBC 0x38 //7<<3 |
||
54 | |||
55 | #define rUSBIRQ 0x68 //13<<3 |
||
56 | /* USBIRQ Bits */ |
||
57 | #define bmVBUSIRQ 0x40 //b6 |
||
58 | #define bmNOVBUSIRQ 0x20 //b5 |
||
59 | #define bmOSCOKIRQ 0x01 //b0 |
||
60 | |||
61 | #define rUSBIEN 0x70 //14<<3 |
||
62 | /* USBIEN Bits */ |
||
63 | #define bmVBUSIE 0x40 //b6 |
||
64 | #define bmNOVBUSIE 0x20 //b5 |
||
65 | #define bmOSCOKIE 0x01 //b0 |
||
66 | |||
67 | #define rUSBCTL 0x78 //15<<3 |
||
68 | /* USBCTL Bits */ |
||
69 | #define bmCHIPRES 0x20 //b5 |
||
70 | #define bmPWRDOWN 0x10 //b4 |
||
71 | |||
72 | #define rCPUCTL 0x80 //16<<3 |
||
73 | /* CPUCTL Bits */ |
||
74 | #define bmPUSLEWID1 0x80 //b7 |
||
75 | #define bmPULSEWID0 0x40 //b6 |
||
76 | #define bmIE 0x01 //b0 |
||
77 | |||
78 | #define rPINCTL 0x88 //17<<3 |
||
79 | /* PINCTL Bits */ |
||
80 | #define bmFDUPSPI 0x10 //b4 |
||
81 | #define bmINTLEVEL 0x08 //b3 |
||
82 | #define bmPOSINT 0x04 //b2 |
||
83 | #define bmGPXB 0x02 //b1 |
||
84 | #define bmGPXA 0x01 //b0 |
||
85 | // GPX pin selections |
||
86 | #define GPX_OPERATE 0x00 |
||
87 | #define GPX_VBDET 0x01 |
||
88 | #define GPX_BUSACT 0x02 |
||
89 | #define GPX_SOF 0x03 |
||
90 | |||
91 | #define rREVISION 0x90 //18<<3 |
||
92 | |||
93 | #define rIOPINS1 0xa0 //20<<3 |
||
94 | |||
95 | /* IOPINS1 Bits */ |
||
96 | #define bmGPOUT0 0x01 |
||
97 | #define bmGPOUT1 0x02 |
||
98 | #define bmGPOUT2 0x04 |
||
99 | #define bmGPOUT3 0x08 |
||
100 | #define bmGPIN0 0x10 |
||
101 | #define bmGPIN1 0x20 |
||
102 | #define bmGPIN2 0x40 |
||
103 | #define bmGPIN3 0x80 |
||
104 | |||
105 | #define rIOPINS2 0xa8 //21<<3 |
||
106 | /* IOPINS2 Bits */ |
||
107 | #define bmGPOUT4 0x01 |
||
108 | #define bmGPOUT5 0x02 |
||
109 | #define bmGPOUT6 0x04 |
||
110 | #define bmGPOUT7 0x08 |
||
111 | #define bmGPIN4 0x10 |
||
112 | #define bmGPIN5 0x20 |
||
113 | #define bmGPIN6 0x40 |
||
114 | #define bmGPIN7 0x80 |
||
115 | |||
116 | #define rGPINIRQ 0xb0 //22<<3 |
||
117 | /* GPINIRQ Bits */ |
||
118 | #define bmGPINIRQ0 0x01 |
||
119 | #define bmGPINIRQ1 0x02 |
||
120 | #define bmGPINIRQ2 0x04 |
||
121 | #define bmGPINIRQ3 0x08 |
||
122 | #define bmGPINIRQ4 0x10 |
||
123 | #define bmGPINIRQ5 0x20 |
||
124 | #define bmGPINIRQ6 0x40 |
||
125 | #define bmGPINIRQ7 0x80 |
||
126 | |||
127 | #define rGPINIEN 0xb8 //23<<3 |
||
128 | /* GPINIEN Bits */ |
||
129 | #define bmGPINIEN0 0x01 |
||
130 | #define bmGPINIEN1 0x02 |
||
131 | #define bmGPINIEN2 0x04 |
||
132 | #define bmGPINIEN3 0x08 |
||
133 | #define bmGPINIEN4 0x10 |
||
134 | #define bmGPINIEN5 0x20 |
||
135 | #define bmGPINIEN6 0x40 |
||
136 | #define bmGPINIEN7 0x80 |
||
137 | |||
138 | #define rGPINPOL 0xc0 //24<<3 |
||
139 | /* GPINPOL Bits */ |
||
140 | #define bmGPINPOL0 0x01 |
||
141 | #define bmGPINPOL1 0x02 |
||
142 | #define bmGPINPOL2 0x04 |
||
143 | #define bmGPINPOL3 0x08 |
||
144 | #define bmGPINPOL4 0x10 |
||
145 | #define bmGPINPOL5 0x20 |
||
146 | #define bmGPINPOL6 0x40 |
||
147 | #define bmGPINPOL7 0x80 |
||
148 | |||
149 | #define rHIRQ 0xc8 //25<<3 |
||
150 | /* HIRQ Bits */ |
||
151 | #define bmBUSEVENTIRQ 0x01 // indicates BUS Reset Done or BUS Resume |
||
152 | #define bmRWUIRQ 0x02 |
||
153 | #define bmRCVDAVIRQ 0x04 |
||
154 | #define bmSNDBAVIRQ 0x08 |
||
155 | #define bmSUSDNIRQ 0x10 |
||
156 | #define bmCONDETIRQ 0x20 |
||
157 | #define bmFRAMEIRQ 0x40 |
||
158 | #define bmHXFRDNIRQ 0x80 |
||
159 | |||
160 | #define rHIEN 0xd0 //26<<3 |
||
161 | /* HIEN Bits */ |
||
162 | #define bmBUSEVENTIE 0x01 |
||
163 | #define bmRWUIE 0x02 |
||
164 | #define bmRCVDAVIE 0x04 |
||
165 | #define bmSNDBAVIE 0x08 |
||
166 | #define bmSUSDNIE 0x10 |
||
167 | #define bmCONDETIE 0x20 |
||
168 | #define bmFRAMEIE 0x40 |
||
169 | #define bmHXFRDNIE 0x80 |
||
170 | |||
171 | #define rMODE 0xd8 //27<<3 |
||
172 | /* MODE Bits */ |
||
173 | #define bmHOST 0x01 |
||
174 | #define bmLOWSPEED 0x02 |
||
175 | #define bmHUBPRE 0x04 |
||
176 | #define bmSOFKAENAB 0x08 |
||
177 | #define bmSEPIRQ 0x10 |
||
178 | #define bmDELAYISO 0x20 |
||
179 | #define bmDMPULLDN 0x40 |
||
180 | #define bmDPPULLDN 0x80 |
||
181 | |||
182 | #define rPERADDR 0xe0 //28<<3 |
||
183 | |||
184 | #define rHCTL 0xe8 //29<<3 |
||
185 | /* HCTL Bits */ |
||
186 | #define bmBUSRST 0x01 |
||
187 | #define bmFRMRST 0x02 |
||
188 | #define bmSAMPLEBUS 0x04 |
||
189 | #define bmSIGRSM 0x08 |
||
190 | #define bmRCVTOG0 0x10 |
||
191 | #define bmRCVTOG1 0x20 |
||
192 | #define bmSNDTOG0 0x40 |
||
193 | #define bmSNDTOG1 0x80 |
||
194 | |||
195 | #define rHXFR 0xf0 //30<<3 |
||
196 | /* Host transfer token values for writing the HXFR register (R30) */ |
||
197 | /* OR this bit field with the endpoint number in bits 3:0 */ |
||
198 | #define tokSETUP 0x10 // HS=0, ISO=0, OUTNIN=0, SETUP=1 |
||
199 | #define tokIN 0x00 // HS=0, ISO=0, OUTNIN=0, SETUP=0 |
||
200 | #define tokOUT 0x20 // HS=0, ISO=0, OUTNIN=1, SETUP=0 |
||
201 | #define tokINHS 0x80 // HS=1, ISO=0, OUTNIN=0, SETUP=0 |
||
202 | #define tokOUTHS 0xA0 // HS=1, ISO=0, OUTNIN=1, SETUP=0 |
||
203 | #define tokISOIN 0x40 // HS=0, ISO=1, OUTNIN=0, SETUP=0 |
||
204 | #define tokISOOUT 0x60 // HS=0, ISO=1, OUTNIN=1, SETUP=0 |
||
205 | |||
206 | #define rHRSL 0xf8 //31<<3 |
||
207 | /* HRSL Bits */ |
||
208 | #define bmRCVTOGRD 0x10 |
||
209 | #define bmSNDTOGRD 0x20 |
||
210 | #define bmKSTATUS 0x40 |
||
211 | #define bmJSTATUS 0x80 |
||
212 | #define bmSE0 0x00 //SE0 - disconnect state |
||
213 | #define bmSE1 0xc0 //SE1 - illegal state |
||
214 | /* Host error result codes, the 4 LSB's in the HRSL register */ |
||
215 | #define hrSUCCESS 0x00 |
||
216 | #define hrBUSY 0x01 |
||
217 | #define hrBADREQ 0x02 |
||
218 | #define hrUNDEF 0x03 |
||
219 | #define hrNAK 0x04 |
||
220 | #define hrSTALL 0x05 |
||
221 | #define hrTOGERR 0x06 |
||
222 | #define hrWRONGPID 0x07 |
||
223 | #define hrBADBC 0x08 |
||
224 | #define hrPIDERR 0x09 |
||
225 | #define hrPKTERR 0x0A |
||
226 | #define hrCRCERR 0x0B |
||
227 | #define hrKERR 0x0C |
||
228 | #define hrJERR 0x0D |
||
229 | #define hrTIMEOUT 0x0E |
||
230 | #define hrBABBLE 0x0F |
||
231 | |||
232 | #define MODE_FS_HOST (bmDPPULLDN|bmDMPULLDN|bmHOST|bmSOFKAENAB) |
||
233 | #define MODE_LS_HOST (bmDPPULLDN|bmDMPULLDN|bmHOST|bmLOWSPEED|bmSOFKAENAB) |
||
234 | |||
235 | |||
236 | #endif //_MAX3421Econstants_h_ |