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| Rev 426 | Rev 434 | ||
|---|---|---|---|
| 1 | #include <avr/io.h> |
1 | #include <avr/io.h> |
| 2 | #include <avr/interrupt.h> |
2 | #include <avr/interrupt.h> |
| 3 | 3 | ||
| 4 | #include "main.h" |
4 | #include "main.h" |
| 5 | #include "uart1.h" |
5 | #include "uart1.h" |
| - | 6 | #include "printf_P.h" |
|
| 6 | #include "ubx.h" |
7 | #include "ubx.h" |
| 7 | 8 | ||
| 8 | 9 | ||
| 9 | /****************************************************************/ |
10 | /****************************************************************/ |
| 10 | /* Initialization of the USART1 */ |
11 | /* Initialization of the USART1 */ |
| 11 | /****************************************************************/ |
12 | /****************************************************************/ |
| 12 | void USART1_Init (void) |
13 | void USART1_Init (void) |
| 13 | { |
14 | { |
| - | 15 | printf("\r\n UART1 init..."); |
|
| 14 | // USART1 Control and Status Register A, B, C and baud rate register |
16 | // USART1 Control and Status Register A, B, C and baud rate register |
| 15 | uint8_t sreg = SREG; |
17 | uint8_t sreg = SREG; |
| 16 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
18 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
| 17 | 19 | ||
| 18 | // disable all interrupts before reconfiguration |
20 | // disable all interrupts before reconfiguration |
| 19 | cli(); |
21 | cli(); |
| 20 | 22 | ||
| 21 | // disable RX-Interrupt |
23 | // disable RX-Interrupt |
| 22 | UCSR1B &= ~(1 << RXCIE1); |
24 | UCSR1B &= ~(1 << RXCIE1); |
| 23 | // disable TX-Interrupt |
25 | // disable TX-Interrupt |
| 24 | UCSR1B &= ~(1 << TXCIE1); |
26 | UCSR1B &= ~(1 << TXCIE1); |
| 25 | // disable DRE-Interrupt |
27 | // disable DRE-Interrupt |
| 26 | UCSR1B &= ~(1 << UDRIE1); |
28 | UCSR1B &= ~(1 << UDRIE1); |
| 27 | 29 | ||
| 28 | // set direction of RXD1 and TXD1 pins |
30 | // set direction of RXD1 and TXD1 pins |
| 29 | // set RXD1 (PD2) as an input pin |
31 | // set RXD1 (PD2) as an input pin |
| 30 | PORTD |= (1 << PORTD2); |
32 | PORTD |= (1 << PORTD2); |
| 31 | DDRD &= ~(1 << DDD2); |
33 | DDRD &= ~(1 << DDD2); |
| 32 | 34 | ||
| 33 | // set TXD1 (PD3) as an output pin |
35 | // set TXD1 (PD3) as an output pin |
| 34 | PORTD |= (1 << PORTD3); |
36 | PORTD |= (1 << PORTD3); |
| 35 | DDRD |= (1 << DDD3); |
37 | DDRD |= (1 << DDD3); |
| 36 | 38 | ||
| 37 | // USART0 Baud Rate Register |
39 | // USART0 Baud Rate Register |
| 38 | // set clock divider |
40 | // set clock divider |
| 39 | UBRR1H = (uint8_t)(ubrr>>8); |
41 | UBRR1H = (uint8_t)(ubrr>>8); |
| 40 | UBRR1L = (uint8_t)ubrr; |
42 | UBRR1L = (uint8_t)ubrr; |
| 41 | 43 | ||
| 42 | // enable double speed operation |
44 | // enable double speed operation |
| 43 | UCSR1A |= (1 << U2X1); |
45 | UCSR1A |= (1 << U2X1); |
| 44 | // enable receiver and transmitter |
46 | // enable receiver and transmitter |
| 45 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
47 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
| 46 | // set asynchronous mode |
48 | // set asynchronous mode |
| 47 | UCSR1C &= ~(1 << UMSEL11); |
49 | UCSR1C &= ~(1 << UMSEL11); |
| 48 | UCSR1C &= ~(1 << UMSEL10); |
50 | UCSR1C &= ~(1 << UMSEL10); |
| 49 | // no parity |
51 | // no parity |
| 50 | UCSR1C &= ~(1 << UPM11); |
52 | UCSR1C &= ~(1 << UPM11); |
| 51 | UCSR1C &= ~(1 << UPM10); |
53 | UCSR1C &= ~(1 << UPM10); |
| 52 | // 1 stop bit |
54 | // 1 stop bit |
| 53 | UCSR1C &= ~(1 << USBS1); |
55 | UCSR1C &= ~(1 << USBS1); |
| 54 | // 8-bit |
56 | // 8-bit |
| 55 | UCSR1B &= ~(1 << UCSZ12); |
57 | UCSR1B &= ~(1 << UCSZ12); |
| 56 | UCSR1C |= (1 << UCSZ11); |
58 | UCSR1C |= (1 << UCSZ11); |
| 57 | UCSR1C |= (1 << UCSZ10); |
59 | UCSR1C |= (1 << UCSZ10); |
| 58 | 60 | ||
| 59 | // flush receive buffer explicit |
61 | // flush receive buffer explicit |
| 60 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
62 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
| 61 | 63 | ||
| 62 | // enable interrupts at the end |
64 | // enable interrupts at the end |
| 63 | // enable RX-Interrupt |
65 | // enable RX-Interrupt |
| 64 | UCSR1B |= (1 << RXCIE1); |
66 | UCSR1B |= (1 << RXCIE1); |
| 65 | // enable TX-Interrupt |
67 | // enable TX-Interrupt |
| 66 | UCSR1B |= (1 << TXCIE1); |
68 | UCSR1B |= (1 << TXCIE1); |
| 67 | // enable DRE interrupt |
69 | // enable DRE interrupt |
| 68 | //UCSR1B |= (1 << UDRIE1); |
70 | //UCSR1B |= (1 << UDRIE1); |
| 69 | 71 | ||
| 70 | 72 | ||
| 71 | // restore global interrupt flags |
73 | // restore global interrupt flags |
| 72 | SREG = sreg; |
74 | SREG = sreg; |
| 73 | 75 | sei(); |
|
| - | 76 | printf("ok"); |
|
| 74 | } |
77 | } |
| 75 | 78 | ||
| 76 | /****************************************************************/ |
79 | /****************************************************************/ |
| 77 | /* USART1 transmitter ISR */ |
80 | /* USART1 transmitter ISR */ |
| 78 | /****************************************************************/ |
81 | /****************************************************************/ |
| 79 | /*ISR(USART1_TX_vect) |
82 | /*ISR(USART1_TX_vect) |
| 80 | { |
83 | { |
| 81 | 84 | ||
| 82 | } |
85 | } |
| 83 | */ |
86 | */ |
| 84 | /****************************************************************/ |
87 | /****************************************************************/ |
| 85 | /* USART1 receiver ISR */ |
88 | /* USART1 receiver ISR */ |
| 86 | /****************************************************************/ |
89 | /****************************************************************/ |
| 87 | ISR(USART1_RX_vect) |
90 | ISR(USART1_RX_vect) |
| 88 | { |
91 | { |
| 89 | uint8_t c; |
92 | uint8_t c; |
| 90 | c = UDR1; // get data byte |
93 | c = UDR1; // get data byte |
| 91 | 94 | ||
| 92 | UBX_Parser(c); // and put it into the ubx protocol parser |
95 | UBX_Parser(c); // and put it into the ubx protocol parser |
| 93 | 96 | ||
| 94 | } |
97 | } |
| 95 | 98 | ||