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| Rev 484 | Rev 489 | ||
|---|---|---|---|
| Line 73... | Line 73... | ||
| 73 | TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms |
73 | TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms |
| 74 | CountMilliseconds++; |
74 | CountMilliseconds++; |
| 75 | if(SD_WatchDog) SD_WatchDog--; |
75 | if(SD_WatchDog) SD_WatchDog--; |
| 76 | if(SPIWatchDog) SPIWatchDog--; |
76 | if(SPIWatchDog) SPIWatchDog--; |
| 77 | if(PollingTimeout) PollingTimeout--; |
77 | if(PollingTimeout) PollingTimeout--; |
| - | 78 | ||
| 78 | // generate SW Interrupt to make a regular timing |
79 | // generate SW Interrupt to make a regular timing |
| 79 | // independent from the mainloop at the lowest IRQ priority |
80 | // independent from the mainloop at the lowest IRQ priority |
| 80 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); // Start this Interrupt |
81 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); |
| 81 | } |
82 | } |
| 82 | // IDISABLE; |
83 | // IDISABLE; |
| Line 83... | Line 84... | ||
| 83 | 84 | ||
| 84 | VIC0->VAR = 0xFF; // write any value to VIC0 Vector address register |
85 | VIC0->VAR = 0xFF; // write any value to VIC0 Vector address register |