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| Rev 378 | Rev 380 | ||
|---|---|---|---|
| Line 172... | Line 172... | ||
| 172 | /********************************************************/ |
172 | /********************************************************/ |
| 173 | /* UART2 Interrupt Handler */ |
173 | /* UART2 Interrupt Handler */ |
| 174 | /********************************************************/ |
174 | /********************************************************/ |
| 175 | void UART2_IRQHandler(void) |
175 | void UART2_IRQHandler(void) |
| 176 | { |
176 | { |
| 177 | IENABLE; |
177 | |
| Line 178... | Line 178... | ||
| 178 | 178 | ||
| 179 | // if receive irq or receive timeout irq has occured |
179 | // if receive irq or receive timeout irq has occured |
| 180 | if((UART_GetITStatus(UART2, UART_IT_Receive) != RESET) || (UART_GetITStatus(UART2, UART_IT_ReceiveTimeOut) != RESET) ) |
180 | if((UART_GetITStatus(UART2, UART_IT_Receive) != RESET) || (UART_GetITStatus(UART2, UART_IT_ReceiveTimeOut) != RESET) ) |
| 181 | { |
181 | { |
| Line 201... | Line 201... | ||
| 201 | UART_ReceiveData(UART2); |
201 | UART_ReceiveData(UART2); |
| 202 | } |
202 | } |
| 203 | } |
203 | } |
| 204 | } // eof receive irq or receive timeout irq |
204 | } // eof receive irq or receive timeout irq |
| Line 205... | Line 205... | ||
| 205 | 205 | ||
| 206 | IDISABLE; |
206 | |
| 207 | VIC1->VAR = 0xFF; // write any value to VIC1 Vector address register |
207 | VIC1->VAR = 0xFF; // write any value to VIC1 Vector address register |
| Line 208... | Line 208... | ||
| 208 | } |
208 | } |
| 209 | 209 | ||