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| Rev 362 | Rev 378 | ||
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| Line 56... | Line 56... | ||
| 56 | #include "91x_lib.h" |
56 | #include "91x_lib.h" |
| 57 | #include "timer1.h" |
57 | #include "timer1.h" |
| 58 | #include "uart1.h" |
58 | #include "uart1.h" |
| 59 | #include "config.h" |
59 | #include "config.h" |
| 60 | #include "main.h" |
60 | #include "main.h" |
| - | 61 | #include "led.h" |
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| Line 61... | Line 62... | ||
| 61 | 62 | ||
| 62 | u32 CountMilliseconds; |
63 | u32 CountMilliseconds; |
| Line 63... | Line 64... | ||
| 63 | DateTime_t SystemTime; |
64 | DateTime_t SystemTime; |
| 64 | 65 | ||
| 65 | //---------------------------------------------------------------------------------------------------- |
66 | //---------------------------------------------------------------------------------------------------- |
| 66 | void TIM1_IRQHandler(void) |
67 | void TIM1_IRQHandler(void) |
| 67 | { |
- | |
| 68 | IENABLE; |
68 | { |
| 69 | 69 | // IENABLE; |
|
| 70 | if(TIM_GetFlagStatus(TIM1, TIM_FLAG_OC1) == SET) |
70 | if(TIM_GetFlagStatus(TIM1, TIM_FLAG_OC1) == SET) |
| 71 | { |
71 | { |
| 72 | TIM_ClearFlag(TIM1, TIM_FLAG_OC1); // clear irq pending bit |
72 | TIM_ClearFlag(TIM1, TIM_FLAG_OC1); // clear irq pending bit |
| 73 | TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms |
73 | TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms |
| 74 | CountMilliseconds++; |
74 | CountMilliseconds++; |
| - | 75 | if(SD_WatchDog) SD_WatchDog--; |
|
| - | 76 | if(SPIWatchDog) SPIWatchDog--; |
|
| 75 | if(SD_WatchDog) SD_WatchDog--; |
77 | if(PollingTimeout) PollingTimeout--; |
| 76 | if(MainWatchDog) MainWatchDog--; |
78 | |
| 77 | // generate SW Interrupt to make a regular timing |
79 | // generate SW Interrupt to make a regular timing |
| 78 | // independent from the mainloop at the lowest IRQ priority |
80 | // independent from the mainloop at the lowest IRQ priority |
| - | 81 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); |
|
| 79 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); |
82 | } |
| 80 | } |
83 | // IDISABLE; |
| 81 | 84 | ||
| Line 82... | Line 85... | ||
| 82 | IDISABLE; |
85 | VIC0->VAR = 0xFF; // write any value to VIC0 Vector address register |
| 83 | } |
86 | } |
| 84 | 87 | ||