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  // Timer/Counter1 Control Register A, B, C
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  // Timer/Counter1 Control Register A, B, C
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  // Normal Mode (bits: WGM13=0, WGM12=0, WGM11=0, WGM10=0)
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  // Normal Mode (bits: WGM13=0, WGM12=0, WGM11=0, WGM10=0)
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  // Compare output pin A & B is disabled (bits: COM1A1=0, COM1A0=0, COM1B1=0, COM1B0=0)
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  // Compare output pin A & B is disabled (bits: COM1A1=0, COM1A0=0, COM1B1=0, COM1B0=0)
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  // Set clock source to SYSCLK/64 (bit: CS12=0, CS11=1, CS10=1)
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  // Set clock source to SYSCLK/8 (bit: CS12=0, CS11=1, CS10=0)
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  // Enable input capture noise cancler (bit: ICNC1=1)
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  // Enable input capture noise cancler (bit: ICNC1=1)
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  // Trigger on positive edge of the input capture pin (bit: ICES1=1),
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  // Trigger on positive edge of the input capture pin (bit: ICES1=1),
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  // Therefore the counter incremets at a clock of 20 MHz/64 = 312.5 kHz or 3.2�s
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  // Therefore the counter incremets at a clock of 20 MHz/64 = 312.5 kHz or 3.2�s
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  // The longest period is 0xFFFF / 312.5 kHz = 0.209712 s.
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  // The longest period is 0xFFFF / 312.5 kHz = 0.209712 s.
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  TCCR1A &= ~((1 << COM1A1) | (1 << COM1A0) | (1 << COM1B1) | (1 << COM1B0) | (1 << WGM11) | (1 << WGM10));
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  TCCR1A &= ~((1<<COM1A1)| (1<<COM1A0) | (1<<COM1B1) | (1<<COM1B0) | (1<<WGM11) | (1<<WGM10));
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  TCCR1B &= ~((1 << WGM13) | (1 << WGM12) | (1 << CS12));
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  TCCR1B &= ~((1<<WGM13) | (1<<WGM12)  | (1<<CS12));
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  TCCR1B |= (1<<CS11)    | (1<<ICNC1);
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  TCCR1C &= ~((1<<FOC1A) | (1<<FOC1B));
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- 
 
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  if (channelMap.RCPolarity) {
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    TCCR1B |= (1<<ICES1);
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  } else {
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  TCCR1B |= (1 << CS11) | (1 << ICES1) | (1 << ICNC1);
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    TCCR1B &= ~(1<<ICES1);
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  TCCR1C &= ~((1 << FOC1A) | (1 << FOC1B));
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  }
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  // Timer/Counter1 Interrupt Mask Register
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  // Timer/Counter1 Interrupt Mask Register
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void RC_calibrate(void) {
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void RC_calibrate(void) {
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  // Do nothing.
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  // Do nothing.
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}
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}
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int16_t RC_getZeroThrottle() {
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int16_t RC_getZeroThrottle(void) {