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| Rev 2050 | Rev 2309 | ||
|---|---|---|---|
| Line 77... | Line 77... | ||
| 77 | UCSR1B &= ~(1 << RXCIE1); |
77 | UCSR1B &= ~(1 << RXCIE1); |
| 78 | // disable TX-Interrupt |
78 | // disable TX-Interrupt |
| 79 | UCSR1B &= ~(1 << TXCIE1); |
79 | UCSR1B &= ~(1 << TXCIE1); |
| 80 | // disable DRE-Interrupt |
80 | // disable DRE-Interrupt |
| 81 | UCSR1B &= ~(1 << UDRIE1); |
81 | UCSR1B &= ~(1 << UDRIE1); |
| - | 82 | /* |
|
| 82 | // set direction of RXD1 and TXD1 pins |
83 | // set direction of RXD1 and TXD1 pins |
| 83 | // set RXD1 (PD2) as an input pin |
84 | // set RXD1 (PD2) as an input pin |
| 84 | PORTD |= (1 << PORTD2); |
85 | PORTD |= (1 << PORTD2); |
| 85 | DDRD &= ~(1 << DDD2); |
86 | DDRD &= ~(1 << DDD2); |
| 86 | - | ||
| 87 | // set TXD1 (PD3) as an output pin |
87 | // set TXD1 (PD3) as an output pin |
| 88 | PORTD |= (1 << PORTD3); |
88 | PORTD |= (1 << PORTD3); |
| 89 | DDRD |= (1 << DDD3); |
89 | DDRD |= (1 << DDD3); |
| 90 | 90 | */ |
|
| 91 | // USART0 Baud Rate Register |
91 | // USART0 Baud Rate Register |
| 92 | // set clock divider |
92 | // set clock divider |
| 93 | UBRR1H = (uint8_t)(ubrr>>8); |
93 | UBRR1H = (uint8_t)(ubrr>>8); |
| 94 | UBRR1L = (uint8_t)ubrr; |
94 | UBRR1L = (uint8_t)ubrr; |
| 95 | // enable double speed operation |
95 | // enable double speed operation |