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| Rev 63 | Rev 73 | ||
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| 62 | 62 | ||
| 63 | // #define PWM_C_ON {TCCR1A = 0x82; TCCR2 = 0x41; PORTB &= ~0x04; DDRB = 0x0E;} |
63 | // #define PWM_C_ON {TCCR1A = 0x82; TCCR2 = 0x41; PORTB &= ~0x04; DDRB = 0x0E;} |
| 64 | // #define PWM_B_ON {TCCR1A = 0x22; TCCR2 = 0x41; PORTB &= ~0x02; DDRB = 0x0E;} |
64 | // #define PWM_B_ON {TCCR1A = 0x22; TCCR2 = 0x41; PORTB &= ~0x02; DDRB = 0x0E;} |
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| 65 | // #define PWM_A_ON {TCCR1A = 0x02; TCCR2 = 0x61; PORTB &= ~0x06; DDRB = 0x0E;} |
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| 66 | 65 | // #define PWM_A_ON {TCCR1A = 0x02; TCCR2 = 0x61; PORTB &= ~0x06; DDRB = 0x0E;} |
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| 67 | 66 | ||
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| 68 | #define PWM_OFF {TCCR1A = 0x01; TCCR2 = 0x41; DDRB = 0x0E; PORTB &= ~0x0E;} |
67 | #define PWM_OFF {OCR1A = 0; OCR1B = 0; OCR2 = 0; TCCR1A = 0x01; TCCR2 = 0x41; DDRB = 0x0E; PORTB &= ~0x0E;} |
| 69 | #endif |
68 | #endif |
| 70 | 69 | ||
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| 76 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
75 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
| 77 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
76 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
| 78 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF; } |
77 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF; } |
| 79 | #define FETS_OFF {PORTD &= ~0x38; PORTB &= ~0x0E; } |
78 | #define FETS_OFF {PORTD &= ~0x38; PORTB &= ~0x0E; } |
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| 80 | 79 | ||
| 81 | #define SENSE_A ADMUX = 0; |
80 | #define SENSE_A ADMUX = 0 | IntRef; |
| 82 | #define SENSE_B ADMUX = 1; |
81 | #define SENSE_B ADMUX = 1 | IntRef; |
| Line 83... | Line 82... | ||
| 83 | #define SENSE_C ADMUX = 2; |
82 | #define SENSE_C ADMUX = 2 | IntRef; |
| 84 | 83 | ||
| 85 | #define ClrSENSE ACSR |= 0x10 |
84 | #define ClrSENSE ACSR |= 0x10 |
| 86 | #define SENSE ((ACSR & 0x10)) |
85 | #define SENSE ((ACSR & 0x10)) |