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| Rev 171 | Rev 195 | ||
|---|---|---|---|
| Line 63... | Line 63... | ||
| 63 | DateTime_t SystemTime; |
63 | DateTime_t SystemTime; |
| Line 64... | Line 64... | ||
| 64 | 64 | ||
| 65 | //---------------------------------------------------------------------------------------------------- |
65 | //---------------------------------------------------------------------------------------------------- |
| 66 | void TIM1_IRQHandler(void) |
66 | void TIM1_IRQHandler(void) |
| - | 67 | { |
|
| - | 68 | IENABLE; |
|
| 67 | { |
69 | |
| 68 | if(TIM_GetFlagStatus(TIM1, TIM_FLAG_OC1) == SET) |
70 | if(TIM_GetFlagStatus(TIM1, TIM_FLAG_OC1) == SET) |
| 69 | { |
71 | { |
| 70 | TIM_ClearFlag(TIM1, TIM_FLAG_OC1); // clear irq pending bit |
72 | TIM_ClearFlag(TIM1, TIM_FLAG_OC1); // clear irq pending bit |
| 71 | TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms |
73 | TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms |
| Line 72... | Line 74... | ||
| 72 | CountMilliseconds++; |
74 | CountMilliseconds++; |
| 73 | 75 | ||
| 74 | // generate SW Interrupt to make a regular timing |
76 | // generate SW Interrupt to make a regular timing |
| 75 | // indeoendent from the mainloop at the lowest IRQ priority |
77 | // independent from the mainloop at the lowest IRQ priority |
| 76 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); |
- | |
| - | 78 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); |
|
| 77 | } |
79 | } |
| 78 | // write any value to VIC0 Vector address register |
80 | |
| Line 79... | Line 81... | ||
| 79 | VIC0->VAR = 0xFF; |
81 | IDISABLE; |
| 80 | } |
82 | } |
| 81 | 83 | ||