Rev 143 | Rev 171 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 143 | Rev 154 | ||
|---|---|---|---|
| Line 93... | Line 93... | ||
| 93 | 93 | ||
| Line 94... | Line 94... | ||
| 94 | u16 pulselen; |
94 | u16 pulselen; |
| 95 | 95 | ||
| - | 96 | if(TIM_GetFlagStatus(TIM2, TIM_FLAG_OC1) == SET) |
|
| 96 | if(TIM_GetFlagStatus(TIM2, TIM_FLAG_OC1) == SET) |
97 | { |
| 97 | { |
98 | TIM_ClearFlag(TIM2, TIM_FLAG_OC1); // clear irq pending bit |
| 98 | if (TIM2->CR1 & CR1_OLVL1_MASK) // start of high pulse |
99 | if (TIM2->CR1 & CR1_OLVL1_MASK) // start of high pulse |
| 99 | { |
100 | { |
| 100 | pulselen = MINSERVOPULSE + SERVORANGE/2; |
101 | pulselen = MINSERVOPULSE + SERVORANGE/2; |
| Line 128... | Line 129... | ||
| 128 | { |
129 | { |
| 129 | pulselen = LowPulseTime1; |
130 | pulselen = LowPulseTime1; |
| 130 | TIM2->CR1 |= CR1_OLVL1_MASK; // make next a high pulse |
131 | TIM2->CR1 |= CR1_OLVL1_MASK; // make next a high pulse |
| 131 | } |
132 | } |
| 132 | TIM2->OC1R += pulselen; |
133 | TIM2->OC1R += pulselen; |
| 133 | TIM_ClearFlag(TIM2, TIM_FLAG_OC1); // clear irq pending bit |
- | |
| 134 | } |
134 | } |
| Line 135... | Line 135... | ||
| 135 | 135 | ||
| 136 | if(TIM_GetFlagStatus(TIM2, TIM_FLAG_OC2) == SET) |
136 | if(TIM_GetFlagStatus(TIM2, TIM_FLAG_OC2) == SET) |
| - | 137 | { |
|
| 137 | { |
138 | TIM_ClearFlag(TIM2, TIM_FLAG_OC2); // clear irq pending bit |
| 138 | if (TIM2->CR1 & CR1_OLVL2_MASK) // was high pulse |
139 | if (TIM2->CR1 & CR1_OLVL2_MASK) // was high pulse |
| 139 | { |
140 | { |
| 140 | pulselen = MINSERVOPULSE + SERVORANGE/2; |
141 | pulselen = MINSERVOPULSE + SERVORANGE/2; |
| 141 | ServoRollOffset = (ServoRollOffset * 3 + (s16)ServoParams.RollControl * MULTIPLYER) / 4; // lowpass offset |
142 | ServoRollOffset = (ServoRollOffset * 3 + (s16)ServoParams.RollControl * MULTIPLYER) / 4; // lowpass offset |
| Line 168... | Line 169... | ||
| 168 | { |
169 | { |
| 169 | pulselen = LowPulseTime2; |
170 | pulselen = LowPulseTime2; |
| 170 | TIM2->CR1 |= CR1_OLVL2_MASK; // make next a high pulse |
171 | TIM2->CR1 |= CR1_OLVL2_MASK; // make next a high pulse |
| 171 | } |
172 | } |
| 172 | TIM2->OC2R += pulselen; |
173 | TIM2->OC2R += pulselen; |
| 173 | TIM_ClearFlag(TIM2, TIM_FLAG_OC2); // clear irq pending bit |
- | |
| 174 | } |
174 | } |
| Line 175... | Line 175... | ||
| 175 | 175 | ||
| 176 | // write any value to VIC0 Vector address register |
176 | // write any value to VIC0 Vector address register |
| 177 | VIC0->VAR = 0xFF; |
177 | VIC0->VAR = 0xFF; |