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| Rev 180 | Rev 195 | ||
|---|---|---|---|
| Line 91... | Line 91... | ||
| 91 | s16 ServoNickValue = 0; |
91 | s16 ServoNickValue = 0; |
| 92 | s16 ServoRollValue = 0; |
92 | s16 ServoRollValue = 0; |
| Line 93... | Line 93... | ||
| 93 | 93 | ||
| Line -... | Line 94... | ||
| - | 94 | u16 pulselen; |
|
| - | 95 | ||
| 94 | u16 pulselen; |
96 | IENABLE; |
| 95 | 97 | ||
| 96 | if(TIM_GetFlagStatus(TIM2, TIM_FLAG_OC1) == SET) |
98 | if(TIM_GetFlagStatus(TIM2, TIM_FLAG_OC1) == SET) |
| 97 | { |
99 | { |
| 98 | TIM_ClearFlag(TIM2, TIM_FLAG_OC1); // clear irq pending bit |
100 | TIM_ClearFlag(TIM2, TIM_FLAG_OC1); // clear irq pending bit |
| Line 171... | Line 173... | ||
| 171 | TIM2->CR1 |= CR1_OLVL2_MASK; // make next a high pulse |
173 | TIM2->CR1 |= CR1_OLVL2_MASK; // make next a high pulse |
| 172 | } |
174 | } |
| 173 | TIM2->OC2R += pulselen; |
175 | TIM2->OC2R += pulselen; |
| 174 | } |
176 | } |
| Line 175... | Line -... | ||
| 175 | - | ||
| 176 | // write any value to VIC0 Vector address register |
177 | |
| 177 | VIC0->VAR = 0xFF; |
178 | IDISABLE; |
| Line 178... | Line 179... | ||
| 178 | } |
179 | } |
| 179 | 180 | ||
| 180 | //---------------------------------------------------------------------------------------------------- |
181 | //---------------------------------------------------------------------------------------------------- |