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| Rev 243 | Rev 244 | ||
|---|---|---|---|
| Line 106... | Line 106... | ||
| 106 | #define UART1_RX_FIFO_LEN 1024 |
106 | #define UART1_RX_FIFO_LEN 1024 |
| 107 | u8 UART1_rxfifobuffer[UART1_RX_FIFO_LEN]; |
107 | u8 UART1_rxfifobuffer[UART1_RX_FIFO_LEN]; |
| 108 | fifo_t UART1_rx_fifo; |
108 | fifo_t UART1_rx_fifo; |
| Line 109... | Line 109... | ||
| 109 | 109 | ||
| 110 | // the rx buffer |
110 | // the rx buffer |
| 111 | #define UART1_RX_BUFFER_LEN 150 |
111 | #define UART1_RX_BUFFER_LEN 200 |
| 112 | u8 UART1_rbuffer[UART1_RX_BUFFER_LEN]; |
112 | u8 UART1_rbuffer[UART1_RX_BUFFER_LEN]; |
| Line 113... | Line 113... | ||
| 113 | Buffer_t UART1_rx_buffer; |
113 | Buffer_t UART1_rx_buffer; |
| 114 | 114 | ||
| 115 | // the tx buffer |
115 | // the tx buffer |
| 116 | #define UART1_TX_BUFFER_LEN 150 |
116 | #define UART1_TX_BUFFER_LEN 200 |
| Line 188... | Line 188... | ||
| 188 | Buffer_Init(&UART1_tx_buffer, UART1_tbuffer, UART1_TX_BUFFER_LEN); |
188 | Buffer_Init(&UART1_tx_buffer, UART1_tbuffer, UART1_TX_BUFFER_LEN); |
| Line 189... | Line 189... | ||
| 189 | 189 | ||
| 190 | // initialize rxd buffer |
190 | // initialize rxd buffer |
| Line 191... | Line 191... | ||
| 191 | Buffer_Init(&UART1_rx_buffer, UART1_rbuffer, UART1_RX_BUFFER_LEN); |
191 | Buffer_Init(&UART1_rx_buffer, UART1_rbuffer, UART1_RX_BUFFER_LEN); |
| 192 | 192 | ||
| Line 193... | Line 193... | ||
| 193 | // initialize the rx fifo |
193 | // initialize the rx fifo, block UART IRQ geting a byte from fifo |
| 194 | fifo_init(&UART1_rx_fifo, UART1_rxfifobuffer, UART1_RX_FIFO_LEN); |
194 | fifo_init(&UART1_rx_fifo, UART1_rxfifobuffer, UART1_RX_FIFO_LEN, NO_ITLine, UART1_ITLine); |
| Line 195... | Line 195... | ||
| 195 | 195 | ||
| Line 238... | Line 238... | ||
| 238 | // enable uart 1 interrupts selective |
238 | // enable uart 1 interrupts selective |
| 239 | UART_ITConfig(UART1, UART_IT_Receive | UART_IT_ReceiveTimeOut, ENABLE); |
239 | UART_ITConfig(UART1, UART_IT_Receive | UART_IT_ReceiveTimeOut, ENABLE); |
| 240 | UART_Cmd(UART1, ENABLE); // enable uart 1 |
240 | UART_Cmd(UART1, ENABLE); // enable uart 1 |
| 241 | // configure the uart 1 interupt line |
241 | // configure the uart 1 interupt line |
| 242 | VIC_Config(UART1_ITLine, VIC_IRQ, PRIORITY_UART1); |
242 | VIC_Config(UART1_ITLine, VIC_IRQ, PRIORITY_UART1); |
| 243 | // enable the uart 1 IRQ |
243 | // enable the uart 1 IRQ |
| 244 | VIC_ITCmd(UART1_ITLine, ENABLE); |
244 | VIC_ITCmd(UART1_ITLine, ENABLE); |
| Line 245... | Line 245... | ||
| 245 | 245 | ||
| 246 | // initialize the debug timer |
246 | // initialize the debug timer |
| 247 | UART1_DebugData_Timer = SetDelay(UART1_DebugData_Interval); |
247 | UART1_DebugData_Timer = SetDelay(UART1_DebugData_Interval); |
| Line 352... | Line 352... | ||
| 352 | if(DebugUART != UART1) return; |
352 | if(DebugUART != UART1) return; |
| Line 353... | Line 353... | ||
| 353 | 353 | ||
| 354 | u8 c; |
354 | u8 c; |
| 355 | // if rx buffer is not locked |
355 | // if rx buffer is not locked |
| - | 356 | if(UART1_rx_buffer.Locked == FALSE) |
|
| 356 | if(UART1_rx_buffer.Locked == FALSE) |
357 | { |
| 357 | { //collect data from primary rx fifo |
358 | //collect data from primary rx fifo |
| - | 359 | while(fifo_get(&UART1_rx_fifo, &c)) |
|
| 358 | while(fifo_get(&UART1_rx_fifo, &c)) |
360 | { |
| 359 | { // break if complete frame is collected |
361 | // break if complete frame is collected |
| 360 | if(MKProtocol_CollectSerialFrame(&UART1_rx_buffer, c)) break; |
362 | if(MKProtocol_CollectSerialFrame(&UART1_rx_buffer, c)) break; |
| 361 | } |
363 | } |
| 362 | } |
364 | } |
| Line 677... | Line 679... | ||
| 677 | UART1_NaviData_Timer = SetDelay(UART1_NaviData_Interval); |
679 | UART1_NaviData_Timer = SetDelay(UART1_NaviData_Interval); |
| 678 | UART1_Request_NaviData = FALSE; |
680 | UART1_Request_NaviData = FALSE; |
| 679 | } |
681 | } |
| 680 | else if( (( (UART1_DebugData_Interval > 0) && CheckDelay(UART1_DebugData_Timer)) || UART1_Request_DebugData) && (UART1_tx_buffer.Locked == FALSE)) |
682 | else if( (( (UART1_DebugData_Interval > 0) && CheckDelay(UART1_DebugData_Timer)) || UART1_Request_DebugData) && (UART1_tx_buffer.Locked == FALSE)) |
| 681 | { |
683 | { |
| 682 | DebugOut.Analog[24] = MagVector.X; |
- | |
| 683 | DebugOut.Analog[25] = MagVector.Y; |
- | |
| 684 | DebugOut.Analog[26] = MagVector.Z; |
- | |
| 685 | MKProtocol_CreateSerialFrame(&UART1_tx_buffer, 'D', NC_ADDRESS, 1,(u8 *)&DebugOut, sizeof(DebugOut)); |
684 | MKProtocol_CreateSerialFrame(&UART1_tx_buffer, 'D', NC_ADDRESS, 1,(u8 *)&DebugOut, sizeof(DebugOut)); |
| 686 | UART1_DebugData_Timer = SetDelay(UART1_DebugData_Interval); |
685 | UART1_DebugData_Timer = SetDelay(UART1_DebugData_Interval); |
| 687 | UART1_Request_DebugData = FALSE; |
686 | UART1_Request_DebugData = FALSE; |
| 688 | } |
687 | } |
| 689 | else if((( (UART1_Data3D_Interval > 0) && CheckDelay(UART1_Data3D_Timer) ) || UART1_Request_Data3D) && (UART1_tx_buffer.Locked == FALSE)) |
688 | else if((( (UART1_Data3D_Interval > 0) && CheckDelay(UART1_Data3D_Timer) ) || UART1_Request_Data3D) && (UART1_tx_buffer.Locked == FALSE)) |