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| Rev 360 | Rev 378 | ||
|---|---|---|---|
| Line 56... | Line 56... | ||
| 56 | #include "91x_lib.h" |
56 | #include "91x_lib.h" |
| 57 | #include "timer2.h" |
57 | #include "timer2.h" |
| 58 | #include "uart1.h" |
58 | #include "uart1.h" |
| 59 | #include "spi_slave.h" |
59 | #include "spi_slave.h" |
| 60 | #include "config.h" |
60 | #include "config.h" |
| - | 61 | #include "led.h" |
|
| Line 61... | Line 62... | ||
| 61 | 62 | ||
| 62 | #define CR1_OLVL1_MASK 0x0100 |
63 | #define CR1_OLVL1_MASK 0x0100 |
| Line 63... | Line 64... | ||
| 63 | #define CR1_OLVL2_MASK 0x0200 |
64 | #define CR1_OLVL2_MASK 0x0200 |
| Line 171... | Line 172... | ||
| 171 | pulselen = LowPulseTime2; |
172 | pulselen = LowPulseTime2; |
| 172 | TIM2->CR1 |= CR1_OLVL2_MASK; // make next a high pulse |
173 | TIM2->CR1 |= CR1_OLVL2_MASK; // make next a high pulse |
| 173 | } |
174 | } |
| 174 | TIM2->OC2R += pulselen; |
175 | TIM2->OC2R += pulselen; |
| 175 | } |
176 | } |
| 176 | - | ||
| 177 | IDISABLE; |
177 | IDISABLE; |
| - | 178 | VIC0->VAR = 0xFF; // write any value to VIC0 Vector address register |
|
| 178 | } |
179 | } |
| Line 179... | Line 180... | ||
| 179 | 180 | ||
| 180 | //---------------------------------------------------------------------------------------------------- |
181 | //---------------------------------------------------------------------------------------------------- |
| 181 | // Servo Timer |
182 | // Servo Timer |
| 182 | //---------------------------------------------------------------------------------------------------- |
183 | //---------------------------------------------------------------------------------------------------- |
| 183 | void TIMER2_Init(void) |
184 | void TIMER2_Init(void) |
| - | 185 | { |
|
| 184 | { |
186 | |
| 185 | GPIO_InitTypeDef GPIO_InitStructure; |
187 | GPIO_InitTypeDef GPIO_InitStructure; |
| Line 186... | Line 188... | ||
| 186 | TIM_InitTypeDef TIM_InitStructure; |
188 | TIM_InitTypeDef TIM_InitStructure; |
| Line 221... | Line 223... | ||
| 221 | TIM_Init(TIM2, &TIM_InitStructure); |
223 | TIM_Init(TIM2, &TIM_InitStructure); |
| Line 222... | Line 224... | ||
| 222 | 224 | ||
| Line 223... | Line 225... | ||
| 223 | TIM_ITConfig(TIM2, TIM_IT_OC1|TIM_IT_OC2, ENABLE); // enable interrupts for the OC 1 & 2 |
225 | TIM_ITConfig(TIM2, TIM_IT_OC1|TIM_IT_OC2, ENABLE); // enable interrupts for the OC 1 & 2 |
| 224 | 226 | ||
| Line 225... | Line 227... | ||
| 225 | VIC_Config(TIM2_ITLine, VIC_IRQ, PRIORITY_TIMER2); |
227 | VIC_Config(TIM2_ITLine, VIC_IRQ, PRIORITY_TIMER2); |
| 226 | VIC_ITCmd(TIM2_ITLine, ENABLE); |
228 | //## VIC_ITCmd(TIM2_ITLine, ENABLE); |
| Line 227... | Line 229... | ||
| 227 | 229 | ||