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| Rev 1796 | Rev 1821 | ||
|---|---|---|---|
| Line 67... | Line 67... | ||
| 67 | #endif |
67 | #endif |
| Line 68... | Line 68... | ||
| 68 | 68 | ||
| 69 | /****************************************************************/ |
69 | /****************************************************************/ |
| 70 | /* Initialization of the USART1 */ |
70 | /* Initialization of the USART1 */ |
| 71 | /****************************************************************/ |
71 | /****************************************************************/ |
| 72 | void usart1_Init (void) { |
72 | void usart1_Init(void) { |
| 73 | // USART1 Control and Status Register A, B, C and baud rate register |
73 | // USART1 Control and Status Register A, B, C and baud rate register |
| 74 | uint8_t sreg = SREG; |
74 | uint8_t sreg = SREG; |
| Line 75... | Line 75... | ||
| 75 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
75 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK / (8 * USART1_BAUD) - 1); |
| 76 | 76 | ||
| Line 77... | Line 77... | ||
| 77 | // disable all interrupts before reconfiguration |
77 | // disable all interrupts before reconfiguration |
| Line 89... | Line 89... | ||
| 89 | PORTD |= (1 << PORTD2); |
89 | PORTD |= (1 << PORTD2); |
| 90 | DDRD &= ~(1 << DDD2); |
90 | DDRD &= ~(1 << DDD2); |
| Line 91... | Line 91... | ||
| 91 | 91 | ||
| 92 | // set TXD1 (PD3) as an output pin |
92 | // set TXD1 (PD3) as an output pin |
| 93 | PORTD |= (1 << PORTD3); |
93 | PORTD |= (1 << PORTD3); |
| Line 94... | Line 94... | ||
| 94 | DDRD |= (1 << DDD3); |
94 | DDRD |= (1 << DDD3); |
| 95 | 95 | ||
| 96 | // USART0 Baud Rate Register |
96 | // USART0 Baud Rate Register |
| 97 | // set clock divider |
97 | // set clock divider |
| Line 98... | Line 98... | ||
| 98 | UBRR1H = (uint8_t)(ubrr>>8); |
98 | UBRR1H = (uint8_t) (ubrr >> 8); |
| 99 | UBRR1L = (uint8_t)ubrr; |
99 | UBRR1L = (uint8_t) ubrr; |
| 100 | 100 | ||
| 101 | // enable double speed operation |
101 | // enable double speed operation |
| Line 110... | Line 110... | ||
| 110 | UCSR1C &= ~(1 << UPM10); |
110 | UCSR1C &= ~(1 << UPM10); |
| 111 | // 1 stop bit |
111 | // 1 stop bit |
| 112 | UCSR1C &= ~(1 << USBS1); |
112 | UCSR1C &= ~(1 << USBS1); |
| 113 | // 8-bit |
113 | // 8-bit |
| 114 | UCSR1B &= ~(1 << UCSZ12); |
114 | UCSR1B &= ~(1 << UCSZ12); |
| 115 | UCSR1C |= (1 << UCSZ11); |
115 | UCSR1C |= (1 << UCSZ11); |
| 116 | UCSR1C |= (1 << UCSZ10); |
116 | UCSR1C |= (1 << UCSZ10); |
| Line 117... | Line 117... | ||
| 117 | 117 | ||
| 118 | // flush receive buffer explicit |
118 | // flush receive buffer explicit |
| - | 119 | while (UCSR1A & (1 << RXC1)) |
|
| Line 119... | Line 120... | ||
| 119 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
120 | UDR1; |
| 120 | 121 | ||
| 121 | // enable interrupts at the end |
122 | // enable interrupts at the end |
| 122 | // enable RX-Interrupt |
123 | // enable RX-Interrupt |
| 123 | UCSR1B |= (1 << RXCIE1); |
124 | UCSR1B |= (1 << RXCIE1); |
| 124 | // enable TX-Interrupt |
125 | // enable TX-Interrupt |
| 125 | //UCSR1B |= (1 << TXCIE1); |
126 | //UCSR1B |= (1 << TXCIE1); |
| Line 126... | Line 127... | ||
| 126 | // enable DRE interrupt |
127 | // enable DRE interrupt |
| 127 | //UCSR1B |= (1 << UDRIE1); |
128 | //UCSR1B |= (1 << UDRIE1); |
| 128 | 129 | ||
| Line 129... | Line 130... | ||
| 129 | // restore global interrupt flags |
130 | // restore global interrupt flags |
| 130 | SREG = sreg; |
131 | SREG = sreg; |
| 131 | } |
132 | } |
| 132 | 133 | ||
| 133 | /****************************************************************/ |
134 | /****************************************************************/ |
| 134 | /* USART1 data register empty ISR */ |
135 | /* USART1 data register empty ISR */ |
| Line 135... | Line 136... | ||
| 135 | /****************************************************************/ |
136 | /****************************************************************/ |
| 136 | /*ISR(USART1_UDRE_vect) { |
137 | /*ISR(USART1_UDRE_vect) { |
| 137 | } |
138 | } |
| 138 | */ |
139 | */ |
| 139 | 140 | ||
| 140 | /****************************************************************/ |
141 | /****************************************************************/ |
| 141 | /* USART1 transmitter ISR */ |
142 | /* USART1 transmitter ISR */ |
| 142 | /****************************************************************/ |
143 | /****************************************************************/ |
| 143 | /*ISR(USART1_TX_vect) { |
144 | /*ISR(USART1_TX_vect) { |
| 144 | } |
145 | } |
| - | 146 | */ |
|
| 145 | */ |
147 | /****************************************************************/ |
| 146 | /****************************************************************/ |
148 | /* USART1 receiver ISR */ |
| 147 | /* USART1 receiver ISR */ |
149 | /****************************************************************/ |
| 148 | /****************************************************************/ |
150 | ISR(USART1_RX_vect) |
| 149 | ISR(USART1_RX_vect) { |
151 | { |
| 150 | uint8_t c; |
152 | uint8_t c; |
| 151 | c = UDR1; // get data byte |
153 | c = UDR1; // get data byte |
| 152 | #ifdef USE_RC_DSL |
154 | #ifdef USE_RC_DSL |
| 153 | dsl_parser(c); // parse dsl data stream |
155 | dsl_parser(c); // parse dsl data stream |