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Line 124... Line 124...
124
#define SPI_TXSYNCBYTE2 0x83
124
#define SPI_TXSYNCBYTE2 0x83
125
#define SPI_RXSYNCBYTE1 0x81
125
#define SPI_RXSYNCBYTE1 0x81
126
#define SPI_RXSYNCBYTE2 0x55
126
#define SPI_RXSYNCBYTE2 0x55
Line 127... Line 127...
127
 
127
 
128
typedef enum {
-
 
129
  SPI_SYNC1,
128
typedef enum {
130
  SPI_SYNC2,
-
 
131
  SPI_DATA
129
        SPI_SYNC1, SPI_SYNC2, SPI_DATA
Line 132... Line 130...
132
} SPI_RXState_t;
130
} SPI_RXState_t;
133
 
131
 
134
// data exchange packets to and From NaviCtrl
132
// data exchange packets to and From NaviCtrl
135
ToNaviCtrl_t                    toNaviCtrl;
133
ToNaviCtrl_t toNaviCtrl;
136
FromNaviCtrl_t                  fromNaviCtrl;
-
 
Line 137... Line 134...
137
SPI_VersionInfo_t               SPI_VersionInfo;
134
FromNaviCtrl_t fromNaviCtrl;
138
 
135
SPI_VersionInfo_t SPI_VersionInfo;
139
 
136
 
140
// rx packet buffer
137
// rx packet buffer
141
#define SPI_RXBUFFER_LEN sizeof(fromNaviCtrl)
138
#define SPI_RXBUFFER_LEN sizeof(fromNaviCtrl)
Line 142... Line 139...
142
uint8_t SPI_RxBuffer[SPI_RXBUFFER_LEN];
139
uint8_t SPI_RxBuffer[SPI_RXBUFFER_LEN];
143
uint8_t SPI_RxBufferIndex = 0;
140
uint8_t SPI_RxBufferIndex = 0;
144
uint8_t SPI_RxBuffer_Request = 0;
141
uint8_t SPI_RxBuffer_Request = 0;
145
 
142
 
Line 146... Line 143...
146
// tx packet buffer
143
// tx packet buffer
147
#define SPI_TXBUFFER_LEN sizeof(toNaviCtrl)
144
#define SPI_TXBUFFER_LEN sizeof(toNaviCtrl)
148
uint8_t *SPI_TxBuffer;
145
uint8_t *SPI_TxBuffer;
149
uint8_t SPI_TxBufferIndex = 0;
146
uint8_t SPI_TxBufferIndex = 0;
Line -... Line 147...
-
 
147
 
150
 
148
uint8_t SPITransferCompleted, SPI_ChkSum;
151
uint8_t SPITransferCompleted, SPI_ChkSum;
149
uint8_t SPI_RxDataValid = 0;
Line 152... Line 150...
152
uint8_t SPI_RxDataValid = 0;
150
uint8_t NCDataOkay = 0;
153
uint8_t NCDataOkay = 0;
151
uint8_t NCSerialDataOkay = 0;
154
uint8_t NCSerialDataOkay = 0;
152
 
155
 
153
uint8_t SPI_CommandSequence[] = { SPI_CMD_USER, SPI_CMD_STICK,
156
uint8_t SPI_CommandSequence[] = { SPI_CMD_USER, SPI_CMD_STICK, SPI_CMD_PARAMETER1, SPI_CMD_STICK, SPI_CMD_MISC, SPI_CMD_VERSION };
154
                SPI_CMD_PARAMETER1, SPI_CMD_STICK, SPI_CMD_MISC, SPI_CMD_VERSION };
157
uint8_t SPI_CommandCounter = 0;
155
uint8_t SPI_CommandCounter = 0;
158
 
156
 
159
/*********************************************/
157
/*********************************************/
160
/*  Initialize SPI interface to NaviCtrl     */
158
/*  Initialize SPI interface to NaviCtrl     */
161
/*********************************************/
159
/*********************************************/
162
void SPI_MasterInit(void) {
160
void SPI_MasterInit(void) {
163
  DDR_SPI |= (1<<DD_MOSI)|(1<<DD_SCK);    // Set MOSI and SCK output, all others input
161
        DDR_SPI |= (1 << DD_MOSI) | (1 << DD_SCK); // Set MOSI and SCK output, all others input
164
  SLAVE_SELECT_DDR_PORT |= (1 << SPI_SLAVE_SELECT); // set Slave select port as output port
162
        SLAVE_SELECT_DDR_PORT |= (1 << SPI_SLAVE_SELECT); // set Slave select port as output port
165
 
163
 
166
  SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR1)|(0<<SPR0)|(0<<SPIE);   // Enable SPI, Master, set clock rate fck/64
164
        SPCR = (1 << SPE) | (1 << MSTR) | (1 << SPR1) | (0 << SPR0) | (0 << SPIE); // Enable SPI, Master, set clock rate fck/64
167
  SPSR = 0;//(1<<SPI2X);
165
        SPSR = 0;//(1<<SPI2X);
168
 
166
 
169
  SLAVE_SELECT_PORT |=  (1 << SPI_SLAVE_SELECT); // Deselect Slave
167
        SLAVE_SELECT_PORT |= (1 << SPI_SLAVE_SELECT); // Deselect Slave
170
 
168
 
171
  SPI_TxBuffer = (uint8_t *) &toNaviCtrl; // set pointer to tx-buffer
169
        SPI_TxBuffer = (uint8_t *) &toNaviCtrl; // set pointer to tx-buffer
172
  SPITransferCompleted = 1;
170
        SPITransferCompleted = 1;
173
  // initialize data packet to NaviControl
171
        // initialize data packet to NaviControl
174
  toNaviCtrl.Sync1 = SPI_TXSYNCBYTE1;
172
        toNaviCtrl.Sync1 = SPI_TXSYNCBYTE1;
175
  toNaviCtrl.Sync2 = SPI_TXSYNCBYTE2;
173
        toNaviCtrl.Sync2 = SPI_TXSYNCBYTE2;
176
 
174
 
177
  toNaviCtrl.Command = SPI_CMD_USER;
175
        toNaviCtrl.Command = SPI_CMD_USER;
178
  toNaviCtrl.IntegralPitch = 0;
176
        toNaviCtrl.IntegralPitch = 0;
179
  toNaviCtrl.IntegralRoll = 0;
177
        toNaviCtrl.IntegralRoll = 0;
180
  NCSerialDataOkay = 0;
178
        NCSerialDataOkay = 0;
181
  NCDataOkay = 0;
179
        NCDataOkay = 0;
182
 
180
 
Line 183... Line 181...
183
  SPI_RxDataValid = 0;
181
        SPI_RxDataValid = 0;
184
 
182
 
185
  SPI_VersionInfo.Major = VERSION_MAJOR;
183
        SPI_VersionInfo.Major = VERSION_MAJOR;
186
  SPI_VersionInfo.Minor = VERSION_MINOR;
184
        SPI_VersionInfo.Minor = VERSION_MINOR;
308
    default:
331
                default:
Line 309... Line 332...
309
      break;
332
                        break;
310
    }
333
                }
311
  } else { // no valid data from NaviCtrl
334
        } else { // no valid data from NaviCtrl
312
      // disable GPS control
335
                // disable GPS control
-
 
336
                GPSStickPitch = 0;
313
      GPSStickPitch = 0;
337
                GPSStickRoll = 0;
314
      GPSStickRoll = 0;
338
        }
315
    }
339
}
316
}
340
 
317
 
341
/*********************************************/
318
/*********************************************/
342
/*  Start Transmission of packet to NaviCtrl */
319
/*  Start Transmission of packet to NaviCtrl */
343
/*********************************************/
320
/*********************************************/
344
void SPI_StartTransmitPacket(void) {
-
 
345
        if (!SPITransferCompleted)
321
void SPI_StartTransmitPacket(void){
346
                return; // return immediately if transfer is in progress
322
  if (!SPITransferCompleted) return; // return immediately if transfer is in progress
347
        else // transmission was completed
323
  else // transmission was completed
348
        {
324
    {
349
                SLAVE_SELECT_PORT &= ~(1 << SPI_SLAVE_SELECT); // Select slave
325
      SLAVE_SELECT_PORT &=  ~(1 << SPI_SLAVE_SELECT);  // Select slave
350
 
326
     
351
                // cyclic commands
327
      // cyclic commands
352
                toNaviCtrl.Command = SPI_CommandSequence[SPI_CommandCounter++];
328
      toNaviCtrl.Command = SPI_CommandSequence[SPI_CommandCounter++];
353
                if (SPI_CommandCounter >= sizeof(SPI_CommandSequence))
329
      if (SPI_CommandCounter >= sizeof(SPI_CommandSequence)) SPI_CommandCounter = 0;
354
                        SPI_CommandCounter = 0;
330
     
355
 
-
 
356
                SPITransferCompleted = 0; // transfer is in progress
-
 
357
                UpdateSPI_Buffer(); // update data in toNaviCtrl
-
 
358
 
-
 
359
                SPI_TxBufferIndex = 1; //proceed with 2nd byte
-
 
360
 
-
 
361
                // -- Debug-Output ---
-
 
362
                //----
-
 
363
                asm volatile ("nop");
-
 
364
                asm volatile ("nop");
-
 
365
                asm volatile ("nop");
-
 
366
                asm volatile ("nop");
-
 
367
                asm volatile ("nop");
-
 
368
                asm volatile ("nop");
-
 
369
                asm volatile ("nop");
-
 
370
                asm volatile ("nop");
-
 
371
                asm volatile ("nop");
-
 
372
                asm volatile ("nop");
-
 
373
                asm volatile ("nop");
-
 
374
                asm volatile ("nop");
-
 
375
                asm volatile ("nop");
-
 
376
                asm volatile ("nop");
331
      SPITransferCompleted = 0; // transfer is in progress
377
                asm volatile ("nop");
332
      UpdateSPI_Buffer();    // update data in toNaviCtrl
378
                asm volatile ("nop");
333
     
379
                asm volatile ("nop");
334
      SPI_TxBufferIndex = 1; //proceed with 2nd byte
380
                asm volatile ("nop");
335
     
381
                asm volatile ("nop");
Line 336... Line 382...
336
      // -- Debug-Output ---
382
                asm volatile ("nop");
337
      //----
383
                asm volatile ("nop");
338
      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");
384
                asm volatile ("nop");
339
      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");
385
                asm volatile ("nop");
Line 340... Line 386...
340
      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");
386
                asm volatile ("nop");
341
      toNaviCtrl.Chksum = toNaviCtrl.Sync1; // init checksum
387
                toNaviCtrl.Chksum = toNaviCtrl.Sync1; // init checksum
342
      SPDR = toNaviCtrl.Sync1; // send first byte
388
                SPDR = toNaviCtrl.Sync1; // send first byte
343
    }
389
        }
344
}
390
}
-
 
391
 
345
 
392
//------------------------------------------------------
-
 
393
// This is the spi data transfer between FlightCtrl and NaviCtrl
346
//------------------------------------------------------
394
// Every time this routine is called within the mainloop one byte of the packet to
347
// This is the spi data transfer between FlightCtrl and NaviCtrl
395
// the NaviCtrl and one byte of the packet from the NaviCtrl is possible transfered
348
// Every time this routine is called within the mainloop one byte of the packet to
396
 
349
// the NaviCtrl and one byte of the packet from the NaviCtrl is possible transfered
397
void SPI_TransmitByte(void) {
350
 
398
        static SPI_RXState_t SPI_RXState = SPI_SYNC1;
351
void SPI_TransmitByte(void) {
399
        uint8_t rxdata;
352
  static SPI_RXState_t SPI_RXState = SPI_SYNC1;
400
        static uint8_t rxchksum;
353
  uint8_t rxdata;
401
 
354
  static uint8_t rxchksum;
402
        if (SPITransferCompleted)
355
 
403
                return; // return immediatly if transfer was completed
356
  if (SPITransferCompleted) return;  // return immediatly if transfer was completed
404
        if (!(SPSR & (1 << SPIF)))
357
  if (!(SPSR & (1 << SPIF))) return; // return if no SPI-IRQ pending
405
                return; // return if no SPI-IRQ pending
358
  SendSPI = 4; // mait 4 * 0.102 ms for the next call of SPI_TransmitByte() in the main loop
-
 
359
 
406
        SendSPI = 4; // mait 4 * 0.102 ms for the next call of SPI_TransmitByte() in the main loop
360
  SLAVE_SELECT_PORT |=  (1 << SPI_SLAVE_SELECT);   // DeselectSlave
407
 
361
 
408
        SLAVE_SELECT_PORT |= (1 << SPI_SLAVE_SELECT); // DeselectSlave
362
  rxdata = SPDR; // save spi data register
409
 
363
 
410
        rxdata = SPDR; // save spi data register
364
  switch (SPI_RXState) {
411
 
365
  case SPI_SYNC1: // first sync byte
-
 
366
    SPI_RxBufferIndex = 0; // set pointer to start of rx buffer
412
        switch (SPI_RXState) {
367
    rxchksum = rxdata; // initialize checksum
413
        case SPI_SYNC1: // first sync byte
368
    if (rxdata == SPI_RXSYNCBYTE1 )
-
 
369
      { // 1st Syncbyte found
414
                SPI_RxBufferIndex = 0; // set pointer to start of rx buffer
370
        SPI_RXState  = SPI_SYNC2; // trigger to state for second sync byte
415
                rxchksum = rxdata; // initialize checksum
371
      }
416
                if (rxdata == SPI_RXSYNCBYTE1) { // 1st Syncbyte found
372
    break;
417
                        SPI_RXState = SPI_SYNC2; // trigger to state for second sync byte
373
   
418
                }
374
  case SPI_SYNC2: // second sync byte
419
                break;
375
    if (rxdata == SPI_RXSYNCBYTE2)
420
 
376
      { // 2nd Syncbyte found
421
        case SPI_SYNC2: // second sync byte
377
        rxchksum += rxdata; // update checksum
422
                if (rxdata == SPI_RXSYNCBYTE2) { // 2nd Syncbyte found
378
        SPI_RXState  = SPI_DATA;   // trigger to state for second sync byte
423
                        rxchksum += rxdata; // update checksum
379
      }
424
                        SPI_RXState = SPI_DATA; // trigger to state for second sync byte
380
    else // 2nd Syncbyte not found
425
                } else // 2nd Syncbyte not found
381
      {
426
                {
382
        SPI_RXState  = SPI_SYNC1; // jump back to 1st sync byte
427
                        SPI_RXState = SPI_SYNC1; // jump back to 1st sync byte
383
      }
428
                }
384
    break;
429
                break;
385
   
430
 
386
  case SPI_DATA: // data bytes
431
        case SPI_DATA: // data bytes
387
    SPI_RxBuffer[SPI_RxBufferIndex++] = rxdata;  // copy data byte to spi buffer
432
                SPI_RxBuffer[SPI_RxBufferIndex++] = rxdata; // copy data byte to spi buffer
388
    // if all bytes are received of a packet from the NaviCtrl
433
                // if all bytes are received of a packet from the NaviCtrl
389
    if (SPI_RxBufferIndex >= SPI_RXBUFFER_LEN) {   // last byte transfered is the checksum of the packet
434
                if (SPI_RxBufferIndex >= SPI_RXBUFFER_LEN) { // last byte transfered is the checksum of the packet
390
        if (rxdata == rxchksum) { // checksum matching?
435
                        if (rxdata == rxchksum) { // checksum matching?
391
            // copy SPI_RxBuffer -> FromFlightCtrl
436
                                // copy SPI_RxBuffer -> FromFlightCtrl
392
            uint8_t *ptr = (uint8_t *)&fromNaviCtrl;
437
                                uint8_t *ptr = (uint8_t *) &fromNaviCtrl;
393
            cli();
438
                                cli();
394
            memcpy(ptr, (uint8_t *) SPI_RxBuffer, sizeof(fromNaviCtrl));
439
                                memcpy(ptr, (uint8_t *) SPI_RxBuffer, sizeof(fromNaviCtrl));
395
            sei();
440
                                sei();
396
            SPI_RxDataValid = 1;
441
                                SPI_RxDataValid = 1;
397
          } else {   // checksum does not match
442
                        } else { // checksum does not match
398
            SPI_RxDataValid = 0; // reset valid flag
443
                                SPI_RxDataValid = 0; // reset valid flag
-
 
444
                        }
-
 
445
                        SPI_RXState = SPI_SYNC1; // reset state sync
-
 
446
                } else { // not all bytes transfered
-
 
447
                        rxchksum += rxdata; // update checksum
-
 
448
                }
-
 
449
                break;
-
 
450
        }// eof switch(SPI_RXState)
-
 
451
 
-
 
452
        // if still some bytes left for transmission to NaviCtrl
-
 
453
        if (SPI_TxBufferIndex < SPI_TXBUFFER_LEN) {
-
 
454
                SLAVE_SELECT_PORT &= ~(1 << SPI_SLAVE_SELECT); // SelectSlave
-
 
455
                asm volatile ("nop");
-
 
456
                asm volatile ("nop");
-
 
457
                asm volatile ("nop");
-
 
458
                asm volatile ("nop");
-
 
459
                asm volatile ("nop");
-
 
460
                asm volatile ("nop");
-
 
461
                asm volatile ("nop");
-
 
462
                asm volatile ("nop");
-
 
463
                asm volatile ("nop");
-
 
464
                asm volatile ("nop");
399
          }
465
                asm volatile ("nop");
400
          SPI_RXState  = SPI_SYNC1; // reset state sync
466
                asm volatile ("nop");
401
    } else { // not all bytes transfered
467
                asm volatile ("nop");
402
          rxchksum += rxdata; // update checksum
468
                asm volatile ("nop");
403
    }
469
                asm volatile ("nop");
404
    break;
470
                asm volatile ("nop");
405
  }// eof switch(SPI_RXState)
471
                asm volatile ("nop");
406
 
472
                asm volatile ("nop");
407
  // if still some bytes left for transmission to NaviCtrl
473
                asm volatile ("nop");
408
  if (SPI_TxBufferIndex < SPI_TXBUFFER_LEN) {
474
                asm volatile ("nop");
409
      SLAVE_SELECT_PORT &=  ~(1 << SPI_SLAVE_SELECT);  // SelectSlave
475
                asm volatile ("nop");
410
      asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop");
476
                asm volatile ("nop");