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| Rev 1960 | Rev 1962 | ||
|---|---|---|---|
| Line 78... | Line 78... | ||
| 78 | 78 | ||
| 79 | // disable all interrupts before reconfiguration |
79 | // disable all interrupts before reconfiguration |
| Line 80... | Line 80... | ||
| 80 | cli(); |
80 | cli(); |
| 81 | 81 | ||
| 82 | // PPM-signal is connected to the Input Capture Pin (PD6) of timer 1 |
82 | // PPM-signal is connected to the Input Capture Pin (PD6) of timer 1 |
| Line 83... | Line 83... | ||
| 83 | DDRD &= ~(1 << DDD6); |
83 | DDRD &= ~(1<<1DDD6); |
| 84 | PORTD |= (1 << PORTD6); |
84 | PORTD |= (1<<1PORTD6); |
| 85 | 85 | ||
| 86 | // Channel 5,6,7 is decoded to servo signals at pin PD5 (J3), PD4(J4), PD3(J5) |
86 | // Channel 5,6,7 is decoded to servo signals at pin PD5 (J3), PD4(J4), PD3(J5) |
| 87 | // set as output |
87 | // set as output |
| Line 88... | Line 88... | ||
| 88 | DDRD |= (1 << DDD5) | (1 << DDD4) | (1 << DDD3); |
88 | DDRD |= (1<<DDD5) | (1<<DDD4) | (1<<DDD3); |
| 89 | // low level |
89 | // low level |
| 90 | PORTD &= ~((1 << PORTD5) | (1 << PORTD4) | (1 << PORTD3)); |
90 | PORTD &= ~((1<<PORTD5) | (1<<PORTD4) | (1<<PORTD3)); |
| 91 | 91 | ||
| 92 | // PD3 can't be used if 2nd UART is activated |
92 | // PD3 can't be used if 2nd UART is activated |
| 93 | // because TXD1 is at that port |
93 | // because TXD1 is at that port |
| Line 94... | Line 94... | ||
| 94 | if (CPUType != ATMEGA644P) { |
94 | if (CPUType != ATMEGA644P) { |
| Line 95... | Line 95... | ||
| 95 | DDRD |= (1 << PORTD3); |
95 | DDRD |= (1<<PORTD3); |
| Line 114... | Line 114... | ||
| 114 | // Timer/Counter1 Interrupt Mask Register |
114 | // Timer/Counter1 Interrupt Mask Register |
| Line 115... | Line 115... | ||
| 115 | 115 | ||
| 116 | // Enable Input Capture Interrupt (bit: ICIE1=1) |
116 | // Enable Input Capture Interrupt (bit: ICIE1=1) |
| 117 | // Disable Output Compare A & B Match Interrupts (bit: OCIE1B=0, OICIE1A=0) |
117 | // Disable Output Compare A & B Match Interrupts (bit: OCIE1B=0, OICIE1A=0) |
| 118 | // Enable Overflow Interrupt (bit: TOIE1=0) |
118 | // Enable Overflow Interrupt (bit: TOIE1=0) |
| 119 | TIMSK1 &= ~((1 << OCIE1B) | (1 << OCIE1A) | (1 << TOIE1)); |
119 | TIMSK1 &= ~((1<<OCIE1B) | (1<<OCIE1A) | (1<<TOIE1)); |
| Line 120... | Line 120... | ||
| 120 | TIMSK1 |= (1 << ICIE1); |
120 | TIMSK1 |= (1<<ICIE1); |
| Line 121... | Line 121... | ||
| 121 | 121 | ||
| 122 | RC_Quality = 0; |
122 | RC_Quality = 0; |
| Line 133... | Line 133... | ||
| 133 | | | | | | | | | | | | |
133 | | | | | | | | | | | | |
| 134 | | | | | | | | | | | | |
134 | | | | | | | | | | | | |
| 135 | ___| |_| |_| |_| |_.............| |________________| |
135 | ___| |_| |_| |_| |_.............| |________________| |
| 136 | <-----><-------><------><--------> <------> <--- |
136 | <-----><-------><------><--------> <------> <--- |
| 137 | t0 t1 t2 t4 tn t0 |
137 | t0 t1 t2 t4 tn t0 |