Rev 687 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 687 | Rev 701 | ||
|---|---|---|---|
| Line 41... | Line 41... | ||
| 41 | // disable receiver and transmitter (will flush the buffers) |
41 | // disable receiver and transmitter (will flush the buffers) |
| 42 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
42 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
| Line 43... | Line 43... | ||
| 43 | 43 | ||
| 44 | // set direction of RXD1 and TXD1 pins |
44 | // set direction of RXD1 and TXD1 pins |
| 45 | // set RXD1 (PD2) as an input pin |
- | |
| 46 | PORTD |= (1 << PORTD2); |
45 | // set RXD1 (PD2) as an input pin |
| - | 46 | DDRD &= ~(1 << DDD2); |
|
| - | 47 | PORTD |= (1 << PORTD2); |
|
| 47 | DDRD &= ~(1 << DDD2); |
48 | |
| - | 49 | // set TXD1 (PD3) as an output pin |
|
| 48 | // set TXD1 (PD3) as an output pin |
50 | DDRD |= (1 << DDD3); |
| 49 | PORTD |= (1 << PORTD3); |
- | |
| Line 50... | Line 51... | ||
| 50 | DDRD |= (1 << DDD3); |
51 | PORTD |= (1 << PORTD3); |
| 51 | 52 | ||
| 52 | // USART0 Baud Rate Register |
53 | // USART0 Baud Rate Register |
| 53 | // set clock divider |
54 | // set clock divider |