| /branches/V0.72p Code Redesign killagreg/spi.c |
|---|
| 61,6 → 61,66 |
| #include "timer0.h" |
| #include "analog.h" |
| //----------------------------------------- |
| #define DDR_SPI DDRB |
| #define DD_SS PB4 |
| #define DD_SCK PB7 |
| #define DD_MOSI PB5 |
| #define DD_MISO PB6 |
| // for compatibility reasons gcc3.x <-> gcc4.x |
| #ifndef SPCR |
| #define SPCR SPCR0 |
| #endif |
| #ifndef SPIE |
| #define SPIE SPIE0 |
| #endif |
| #ifndef SPE |
| #define SPE SPE0 |
| #endif |
| #ifndef DORD |
| #define DORD DORD0 |
| #endif |
| #ifndef MSTR |
| #define MSTR MSTR0 |
| #endif |
| #ifndef CPOL |
| #define CPOL CPOL0 |
| #endif |
| #ifndef CPHA |
| #define CPHA CPHA0 |
| #endif |
| #ifndef SPR1 |
| #define SPR1 SPR01 |
| #endif |
| #ifndef SPR0 |
| #define SPR0 SPR00 |
| #endif |
| #ifndef SPDR |
| #define SPDR SPDR0 |
| #endif |
| #ifndef SPSR |
| #define SPSR SPSR0 |
| #endif |
| #ifndef SPIF |
| #define SPIF SPIF0 |
| #endif |
| #ifndef WCOL |
| #define WCOL WCOL0 |
| #endif |
| #ifndef SPI2X |
| #define SPI2X SPI2X0 |
| #endif |
| // ------------------------- |
| #define SLAVE_SELECT_DDR_PORT DDRC |
| #define SLAVE_SELECT_PORT PORTC |
| #define SPI_SLAVE_SELECT PC5 |
| #define SPI_TXSYNCBYTE1 0xAA |
| #define SPI_TXSYNCBYTE2 0x83 |
| #define SPI_RXSYNCBYTE1 0x81 |
| /branches/V0.72p Code Redesign killagreg/spi.h |
|---|
| 8,65 → 8,7 |
| #define SPI_PROTOCOL_COMP 1 |
| //----------------------------------------- |
| #define DDR_SPI DDRB |
| #define DD_SS PB4 |
| #define DD_SCK PB7 |
| #define DD_MOSI PB5 |
| #define DD_MISO PB6 |
| // for compatibility reasons gcc3.x <-> gcc4.x |
| #ifndef SPCR |
| #define SPCR SPCR0 |
| #endif |
| #ifndef SPIE |
| #define SPIE SPIE0 |
| #endif |
| #ifndef SPE |
| #define SPE SPE0 |
| #endif |
| #ifdef DORD |
| #define DORD DORD0 |
| #endif |
| #ifndef MSTR |
| #define MSTR MSTR0 |
| #endif |
| #ifndef CPOL |
| #define CPOL CPOL0 |
| #endif |
| #ifndef CPHA |
| #define CPHA CPHA0 |
| #endif |
| #ifndef SPR1 |
| #define SPR1 SPR01 |
| #endif |
| #ifndef SPR0 |
| #define SPR0 SPR00 |
| #endif |
| #ifndef SPDR |
| #define SPDR SPDR0 |
| #endif |
| #ifndef SPSR |
| #define SPSR SPSR0 |
| #endif |
| #ifndef SPIF |
| #define SPIF SPIF0 |
| #endif |
| #ifndef WCOL |
| #define WCOL WCOL0 |
| #endif |
| #ifndef SPI2X |
| #define SPI2X SPI2X0 |
| #endif |
| // ------------------------- |
| #define SLAVE_SELECT_DDR_PORT DDRC |
| #define SLAVE_SELECT_PORT PORTC |
| #define SPI_SLAVE_SELECT PC5 |
| #define SPI_CMD_USER 10 |
| #define SPI_CMD_STICK 11 |
| #define SPI_CMD_MISC 12 |