| /branches/V0.68d Code Redesign killagreg/uart1.c |
|---|
| 43,11 → 43,12 |
| // set direction of RXD1 and TXD1 pins |
| // set RXD1 (PD2) as an input pin |
| DDRD &= ~(1 << DDD2); |
| PORTD |= (1 << PORTD2); |
| DDRD &= ~(1 << DDD2); |
| // set TXD1 (PD3) as an output pin |
| DDRD |= (1 << DDD3); |
| PORTD |= (1 << PORTD3); |
| DDRD |= (1 << DDD3); |
| // USART0 Baud Rate Register |
| // set clock divider |