| 0,0 → 1,3446 |
|---|
| |
| BrushLess-Ctrl_V0_37.elf: Dateiformat elf32-avr |
| |
| Sektionen: |
| Idx Name Größe VMA LMA Datei-Off Ausr. |
| 0 .text 000019ee 00000000 00000000 00000094 2**0 |
| CONTENTS, ALLOC, LOAD, READONLY, CODE |
| 1 .data 00000016 00800060 000019ee 00001a82 2**0 |
| CONTENTS, ALLOC, LOAD, DATA |
| 2 .bss 00000332 00800076 00800076 00001a98 2**0 |
| ALLOC |
| 3 .stab 000045d8 00000000 00000000 00001a98 2**2 |
| CONTENTS, READONLY, DEBUGGING |
| 4 .stabstr 00001ed5 00000000 00000000 00006070 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| Disassemblierung der Sektion .text: |
| |
| 00000000 <__vectors>: |
| 0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end> |
| 2: f3 c7 rjmp .+4070 ; 0xfea <__vector_1> |
| 4: 2a c0 rjmp .+84 ; 0x5a <__bad_interrupt> |
| 6: 29 c0 rjmp .+82 ; 0x5a <__bad_interrupt> |
| 8: 91 c0 rjmp .+290 ; 0x12c <__vector_4> |
| a: 56 c7 rjmp .+3756 ; 0xeb8 <__vector_5> |
| c: 26 c0 rjmp .+76 ; 0x5a <__bad_interrupt> |
| e: 25 c0 rjmp .+74 ; 0x5a <__bad_interrupt> |
| 10: 42 c7 rjmp .+3716 ; 0xe96 <__vector_8> |
| 12: fa c7 rjmp .+4084 ; 0x1008 <__vector_9> |
| 14: 22 c0 rjmp .+68 ; 0x5a <__bad_interrupt> |
| 16: fa c9 rjmp .-3084 ; 0xfffff40c <__eeprom_end+0xff7ef40c> |
| 18: 20 c0 rjmp .+64 ; 0x5a <__bad_interrupt> |
| 1a: cc c8 rjmp .-3688 ; 0xfffff1b4 <__eeprom_end+0xff7ef1b4> |
| 1c: 1e c0 rjmp .+60 ; 0x5a <__bad_interrupt> |
| 1e: 1d c0 rjmp .+58 ; 0x5a <__bad_interrupt> |
| 20: f2 c0 rjmp .+484 ; 0x206 <__vector_16> |
| 22: 77 c8 rjmp .-3858 ; 0xfffff112 <__eeprom_end+0xff7ef112> |
| 24: 1a c0 rjmp .+52 ; 0x5a <__bad_interrupt> |
| |
| 00000026 <__ctors_end>: |
| 26: 11 24 eor r1, r1 |
| 28: 1f be out 0x3f, r1 ; 63 |
| 2a: cf e5 ldi r28, 0x5F ; 95 |
| 2c: d4 e0 ldi r29, 0x04 ; 4 |
| 2e: de bf out 0x3e, r29 ; 62 |
| 30: cd bf out 0x3d, r28 ; 61 |
| |
| 00000032 <__do_copy_data>: |
| 32: 10 e0 ldi r17, 0x00 ; 0 |
| 34: a0 e6 ldi r26, 0x60 ; 96 |
| 36: b0 e0 ldi r27, 0x00 ; 0 |
| 38: ee ee ldi r30, 0xEE ; 238 |
| 3a: f9 e1 ldi r31, 0x19 ; 25 |
| 3c: 02 c0 rjmp .+4 ; 0x42 <.do_copy_data_start> |
| |
| 0000003e <.do_copy_data_loop>: |
| 3e: 05 90 lpm r0, Z+ |
| 40: 0d 92 st X+, r0 |
| |
| 00000042 <.do_copy_data_start>: |
| 42: a6 37 cpi r26, 0x76 ; 118 |
| 44: b1 07 cpc r27, r17 |
| 46: d9 f7 brne .-10 ; 0x3e <__SP_H__> |
| |
| 00000048 <__do_clear_bss>: |
| 48: 13 e0 ldi r17, 0x03 ; 3 |
| 4a: a6 e7 ldi r26, 0x76 ; 118 |
| 4c: b0 e0 ldi r27, 0x00 ; 0 |
| 4e: 01 c0 rjmp .+2 ; 0x52 <.do_clear_bss_start> |
| |
| 00000050 <.do_clear_bss_loop>: |
| 50: 1d 92 st X+, r1 |
| |
| 00000052 <.do_clear_bss_start>: |
| 52: a8 3a cpi r26, 0xA8 ; 168 |
| 54: b1 07 cpc r27, r17 |
| 56: e1 f7 brne .-8 ; 0x50 <.do_clear_bss_loop> |
| 58: ad c5 rjmp .+2906 ; 0xbb4 <main> |
| |
| 0000005a <__bad_interrupt>: |
| 5a: d2 cf rjmp .-92 ; 0x0 <__heap_end> |
| |
| 0000005c <ADC_Init>: |
| //Init ADC |
| void ADC_Init(void) |
| //############################################################################ |
| { |
| ADCSRA = 0xA6; // Free Run & 1MHZ |
| 5c: 86 ea ldi r24, 0xA6 ; 166 |
| 5e: 86 b9 out 0x06, r24 ; 6 |
| ADMUX = 7; // Kanal 7 |
| 60: 87 e0 ldi r24, 0x07 ; 7 |
| 62: 87 b9 out 0x07, r24 ; 7 |
| ADCSRA |= 0x40; // Start |
| 64: 36 9a sbi 0x06, 6 ; 6 |
| 66: 08 95 ret |
| |
| 00000068 <AdConvert>: |
| } |
| |
| //############################################################################ |
| //Strom Analogwerte lesen |
| void AdConvert(void) |
| //############################################################################ |
| { |
| unsigned int i=0; |
| unsigned char sense; |
| sense = ADMUX; // Sense-Kanal merken |
| 68: 27 b1 in r18, 0x07 ; 7 |
| ADMUX = 0x06; // Kanal 6 |
| 6a: 96 e0 ldi r25, 0x06 ; 6 |
| 6c: 97 b9 out 0x07, r25 ; 7 |
| SFIOR = 0x00; // Analog Comperator aus |
| 6e: 10 be out 0x30, r1 ; 48 |
| ADCSRA = 0xD3; // Converter ein, single |
| 70: 83 ed ldi r24, 0xD3 ; 211 |
| 72: 86 b9 out 0x06, r24 ; 6 |
| ADCSRA |= 0x10; // Ready löschen |
| 74: 34 9a sbi 0x06, 4 ; 6 |
| ADMUX = 0x06; // Kanal 6 |
| 76: 97 b9 out 0x07, r25 ; 7 |
| ADCSRA |= 0x40; // Start |
| 78: 36 9a sbi 0x06, 6 ; 6 |
| while (((ADCSRA & 0x10) == 0)); |
| 7a: 34 9b sbis 0x06, 4 ; 6 |
| 7c: fe cf rjmp .-4 ; 0x7a <AdConvert+0x12> |
| ADMUX = sense; // zurück auf den Sense-Kanal |
| 7e: 27 b9 out 0x07, r18 ; 7 |
| i = ADCW * 4; |
| 80: 84 b1 in r24, 0x04 ; 4 |
| 82: 95 b1 in r25, 0x05 ; 5 |
| // if(i > 300) i = 300; |
| Strom = (i + Strom * 7) / 8; |
| 84: 20 91 7b 00 lds r18, 0x007B |
| 88: 30 91 7c 00 lds r19, 0x007C |
| 8c: a9 01 movw r20, r18 |
| 8e: 63 e0 ldi r22, 0x03 ; 3 |
| 90: 44 0f add r20, r20 |
| 92: 55 1f adc r21, r21 |
| 94: 6a 95 dec r22 |
| 96: e1 f7 brne .-8 ; 0x90 <AdConvert+0x28> |
| 98: 42 1b sub r20, r18 |
| 9a: 53 0b sbc r21, r19 |
| 9c: 88 0f add r24, r24 |
| 9e: 99 1f adc r25, r25 |
| a0: 88 0f add r24, r24 |
| a2: 99 1f adc r25, r25 |
| a4: 48 0f add r20, r24 |
| a6: 59 1f adc r21, r25 |
| a8: 83 e0 ldi r24, 0x03 ; 3 |
| aa: 56 95 lsr r21 |
| ac: 47 95 ror r20 |
| ae: 8a 95 dec r24 |
| b0: e1 f7 brne .-8 ; 0xaa <AdConvert+0x42> |
| b2: 50 93 7c 00 sts 0x007C, r21 |
| b6: 40 93 7b 00 sts 0x007B, r20 |
| if (Strom_max < Strom) Strom_max = Strom; |
| ba: 80 91 7d 00 lds r24, 0x007D |
| be: 99 27 eor r25, r25 |
| c0: 84 17 cp r24, r20 |
| c2: 95 07 cpc r25, r21 |
| c4: 10 f4 brcc .+4 ; 0xca <AdConvert+0x62> |
| c6: 40 93 7d 00 sts 0x007D, r20 |
| ADCSRA = 0x00; |
| ca: 16 b8 out 0x06, r1 ; 6 |
| SFIOR = 0x08; // Analog Comperator ein |
| cc: 88 e0 ldi r24, 0x08 ; 8 |
| ce: 80 bf out 0x30, r24 ; 48 |
| d0: 08 95 ret |
| |
| 000000d2 <MessAD>: |
| } |
| |
| |
| |
| //############################################################################ |
| //Strom Analogwerte lesen |
| unsigned int MessAD(unsigned char channel) |
| //############################################################################ |
| { |
| unsigned char sense; |
| sense = ADMUX; // Sense-Kanal merken |
| d2: 27 b1 in r18, 0x07 ; 7 |
| ADMUX = channel; // Kanal 6 |
| d4: 87 b9 out 0x07, r24 ; 7 |
| SFIOR = 0x00; // Analog Comperator aus |
| d6: 10 be out 0x30, r1 ; 48 |
| ADCSRA = 0xD3; // Converter ein, single |
| d8: 93 ed ldi r25, 0xD3 ; 211 |
| da: 96 b9 out 0x06, r25 ; 6 |
| ADCSRA |= 0x10; // Ready löschen |
| dc: 34 9a sbi 0x06, 4 ; 6 |
| ADMUX = channel; // Kanal 6 |
| de: 87 b9 out 0x07, r24 ; 7 |
| ADCSRA |= 0x40; // Start |
| e0: 36 9a sbi 0x06, 6 ; 6 |
| while (((ADCSRA & 0x10) == 0)); |
| e2: 34 9b sbis 0x06, 4 ; 6 |
| e4: fe cf rjmp .-4 ; 0xe2 <MessAD+0x10> |
| ADMUX = sense; // zurück auf den Sense-Kanal |
| e6: 27 b9 out 0x07, r18 ; 7 |
| ADCSRA = 0x00; |
| e8: 16 b8 out 0x06, r1 ; 6 |
| SFIOR = 0x08; // Analog Comperator ein |
| ea: 88 e0 ldi r24, 0x08 ; 8 |
| ec: 80 bf out 0x30, r24 ; 48 |
| return(ADCW); |
| ee: 84 b1 in r24, 0x04 ; 4 |
| f0: 95 b1 in r25, 0x05 ; 5 |
| f2: 08 95 ret |
| |
| 000000f4 <FastADConvert>: |
| } |
| |
| //############################################################################ |
| //Strom Analogwerte lesen |
| void FastADConvert(void) |
| //############################################################################ |
| { |
| unsigned int i=0; |
| i = MessAD(6) * 4; |
| f4: 86 e0 ldi r24, 0x06 ; 6 |
| f6: ed df rcall .-38 ; 0xd2 <MessAD> |
| f8: 9c 01 movw r18, r24 |
| fa: 22 0f add r18, r18 |
| fc: 33 1f adc r19, r19 |
| fe: 22 0f add r18, r18 |
| 100: 33 1f adc r19, r19 |
| 102: 29 3c cpi r18, 0xC9 ; 201 |
| 104: 31 05 cpc r19, r1 |
| 106: 10 f0 brcs .+4 ; 0x10c <FastADConvert+0x18> |
| 108: 28 ec ldi r18, 0xC8 ; 200 |
| 10a: 30 e0 ldi r19, 0x00 ; 0 |
| // i = ADCW * 4; |
| if(i > 200) i = 200; |
| Strom = i;//(i + Strom * 1) / 2; |
| 10c: 30 93 7c 00 sts 0x007C, r19 |
| 110: 20 93 7b 00 sts 0x007B, r18 |
| if (Strom_max < Strom) Strom_max = Strom; |
| 114: 80 91 7d 00 lds r24, 0x007D |
| 118: 99 27 eor r25, r25 |
| 11a: 82 17 cp r24, r18 |
| 11c: 93 07 cpc r25, r19 |
| 11e: 10 f4 brcc .+4 ; 0x124 <FastADConvert+0x30> |
| 120: 20 93 7d 00 sts 0x007D, r18 |
| ADCSRA = 0x00; |
| 124: 16 b8 out 0x06, r1 ; 6 |
| SFIOR = 0x08; // Analog Comperator ein |
| 126: 88 e0 ldi r24, 0x08 ; 8 |
| 128: 80 bf out 0x30, r24 ; 48 |
| 12a: 08 95 ret |
| |
| 0000012c <__vector_4>: |
| 12c: 1f 92 push r1 |
| 12e: 0f 92 push r0 |
| 130: 0f b6 in r0, 0x3f ; 63 |
| 132: 0f 92 push r0 |
| 134: 11 24 eor r1, r1 |
| 136: 0f 90 pop r0 |
| 138: 0f be out 0x3f, r0 ; 63 |
| 13a: 0f 90 pop r0 |
| 13c: 1f 90 pop r1 |
| 13e: 18 95 reti |
| |
| 00000140 <Manuell>: |
| } |
| 140: 90 91 76 00 lds r25, 0x0076 |
| 144: 92 30 cpi r25, 0x02 ; 2 |
| 146: 41 f1 breq .+80 ; 0x198 <Manuell+0x58> |
| 148: 93 30 cpi r25, 0x03 ; 3 |
| 14a: 30 f4 brcc .+12 ; 0x158 <Manuell+0x18> |
| 14c: 99 23 and r25, r25 |
| 14e: 61 f0 breq .+24 ; 0x168 <Manuell+0x28> |
| 150: 91 30 cpi r25, 0x01 ; 1 |
| 152: 09 f0 breq .+2 ; 0x156 <Manuell+0x16> |
| 154: 57 c0 rjmp .+174 ; 0x204 <Manuell+0xc4> |
| 156: 14 c0 rjmp .+40 ; 0x180 <Manuell+0x40> |
| 158: 94 30 cpi r25, 0x04 ; 4 |
| 15a: c1 f1 breq .+112 ; 0x1cc <Manuell+0x8c> |
| 15c: 94 30 cpi r25, 0x04 ; 4 |
| 15e: 40 f1 brcs .+80 ; 0x1b0 <Manuell+0x70> |
| 160: 95 30 cpi r25, 0x05 ; 5 |
| 162: 09 f0 breq .+2 ; 0x166 <Manuell+0x26> |
| 164: 4f c0 rjmp .+158 ; 0x204 <Manuell+0xc4> |
| 166: 42 c0 rjmp .+132 ; 0x1ec <Manuell+0xac> |
| 168: 81 ea ldi r24, 0xA1 ; 161 |
| 16a: 8f bd out 0x2f, r24 ; 47 |
| 16c: 81 e6 ldi r24, 0x61 ; 97 |
| 16e: 85 bd out 0x25, r24 ; 37 |
| 170: 88 e0 ldi r24, 0x08 ; 8 |
| 172: 87 bb out 0x17, r24 ; 23 |
| 174: 82 b3 in r24, 0x12 ; 18 |
| 176: 87 7d andi r24, 0xD7 ; 215 |
| 178: 82 bb out 0x12, r24 ; 18 |
| 17a: 94 9a sbi 0x12, 4 ; 18 |
| 17c: 82 e0 ldi r24, 0x02 ; 2 |
| 17e: 31 c0 rjmp .+98 ; 0x1e2 <Manuell+0xa2> |
| 180: 81 ea ldi r24, 0xA1 ; 161 |
| 182: 8f bd out 0x2f, r24 ; 47 |
| 184: 81 e6 ldi r24, 0x61 ; 97 |
| 186: 85 bd out 0x25, r24 ; 37 |
| 188: 88 e0 ldi r24, 0x08 ; 8 |
| 18a: 87 bb out 0x17, r24 ; 23 |
| 18c: 82 b3 in r24, 0x12 ; 18 |
| 18e: 87 7e andi r24, 0xE7 ; 231 |
| 190: 82 bb out 0x12, r24 ; 18 |
| 192: 95 9a sbi 0x12, 5 ; 18 |
| 194: 97 b9 out 0x07, r25 ; 7 |
| 196: 18 c0 rjmp .+48 ; 0x1c8 <Manuell+0x88> |
| 198: 81 ea ldi r24, 0xA1 ; 161 |
| 19a: 8f bd out 0x2f, r24 ; 47 |
| 19c: 81 e6 ldi r24, 0x61 ; 97 |
| 19e: 85 bd out 0x25, r24 ; 37 |
| 1a0: 84 e0 ldi r24, 0x04 ; 4 |
| 1a2: 87 bb out 0x17, r24 ; 23 |
| 1a4: 82 b3 in r24, 0x12 ; 18 |
| 1a6: 87 7e andi r24, 0xE7 ; 231 |
| 1a8: 82 bb out 0x12, r24 ; 18 |
| 1aa: 95 9a sbi 0x12, 5 ; 18 |
| 1ac: 17 b8 out 0x07, r1 ; 7 |
| 1ae: 1a c0 rjmp .+52 ; 0x1e4 <Manuell+0xa4> |
| 1b0: 81 ea ldi r24, 0xA1 ; 161 |
| 1b2: 8f bd out 0x2f, r24 ; 47 |
| 1b4: 81 e6 ldi r24, 0x61 ; 97 |
| 1b6: 85 bd out 0x25, r24 ; 37 |
| 1b8: 84 e0 ldi r24, 0x04 ; 4 |
| 1ba: 87 bb out 0x17, r24 ; 23 |
| 1bc: 82 b3 in r24, 0x12 ; 18 |
| 1be: 8f 7c andi r24, 0xCF ; 207 |
| 1c0: 82 bb out 0x12, r24 ; 18 |
| 1c2: 93 9a sbi 0x12, 3 ; 18 |
| 1c4: 82 e0 ldi r24, 0x02 ; 2 |
| 1c6: 87 b9 out 0x07, r24 ; 7 |
| 1c8: 40 98 cbi 0x08, 0 ; 8 |
| 1ca: 08 95 ret |
| 1cc: 81 ea ldi r24, 0xA1 ; 161 |
| 1ce: 8f bd out 0x2f, r24 ; 47 |
| 1d0: 81 e6 ldi r24, 0x61 ; 97 |
| 1d2: 85 bd out 0x25, r24 ; 37 |
| 1d4: 82 e0 ldi r24, 0x02 ; 2 |
| 1d6: 87 bb out 0x17, r24 ; 23 |
| 1d8: 82 b3 in r24, 0x12 ; 18 |
| 1da: 8f 7c andi r24, 0xCF ; 207 |
| 1dc: 82 bb out 0x12, r24 ; 18 |
| 1de: 93 9a sbi 0x12, 3 ; 18 |
| 1e0: 81 e0 ldi r24, 0x01 ; 1 |
| 1e2: 87 b9 out 0x07, r24 ; 7 |
| 1e4: 88 b1 in r24, 0x08 ; 8 |
| 1e6: 83 60 ori r24, 0x03 ; 3 |
| 1e8: 88 b9 out 0x08, r24 ; 8 |
| 1ea: 08 95 ret |
| 1ec: 81 ea ldi r24, 0xA1 ; 161 |
| 1ee: 8f bd out 0x2f, r24 ; 47 |
| 1f0: 81 e6 ldi r24, 0x61 ; 97 |
| 1f2: 85 bd out 0x25, r24 ; 37 |
| 1f4: 82 e0 ldi r24, 0x02 ; 2 |
| 1f6: 87 bb out 0x17, r24 ; 23 |
| 1f8: 82 b3 in r24, 0x12 ; 18 |
| 1fa: 87 7d andi r24, 0xD7 ; 215 |
| 1fc: 82 bb out 0x12, r24 ; 18 |
| 1fe: 94 9a sbi 0x12, 4 ; 18 |
| 200: 17 b8 out 0x07, r1 ; 7 |
| 202: 40 98 cbi 0x08, 0 ; 8 |
| 204: 08 95 ret |
| |
| 00000206 <__vector_16>: |
| 206: 1f 92 push r1 |
| 208: 0f 92 push r0 |
| 20a: 0f b6 in r0, 0x3f ; 63 |
| 20c: 0f 92 push r0 |
| 20e: 11 24 eor r1, r1 |
| 210: 0f 93 push r16 |
| 212: 1f 93 push r17 |
| 214: 2f 93 push r18 |
| 216: 3f 93 push r19 |
| 218: 4f 93 push r20 |
| 21a: 5f 93 push r21 |
| 21c: 6f 93 push r22 |
| 21e: 7f 93 push r23 |
| 220: 8f 93 push r24 |
| 222: 9f 93 push r25 |
| 224: af 93 push r26 |
| 226: bf 93 push r27 |
| 228: ef 93 push r30 |
| 22a: ff 93 push r31 |
| 22c: 88 b1 in r24, 0x08 ; 8 |
| 22e: 99 27 eor r25, r25 |
| 230: 68 94 set |
| 232: 14 f8 bld r1, 4 |
| 234: 96 95 lsr r25 |
| 236: 87 95 ror r24 |
| 238: 16 94 lsr r1 |
| 23a: e1 f7 brne .-8 ; 0x234 <__vector_16+0x2e> |
| 23c: 08 2f mov r16, r24 |
| 23e: 01 70 andi r16, 0x01 ; 1 |
| 240: 10 91 76 00 lds r17, 0x0076 |
| 244: 12 30 cpi r17, 0x02 ; 2 |
| 246: 09 f4 brne .+2 ; 0x24a <__vector_16+0x44> |
| 248: 54 c0 rjmp .+168 ; 0x2f2 <__vector_16+0xec> |
| 24a: 13 30 cpi r17, 0x03 ; 3 |
| 24c: 30 f4 brcc .+12 ; 0x25a <__vector_16+0x54> |
| 24e: 11 23 and r17, r17 |
| 250: 71 f0 breq .+28 ; 0x26e <__vector_16+0x68> |
| 252: 11 30 cpi r17, 0x01 ; 1 |
| 254: 09 f0 breq .+2 ; 0x258 <__vector_16+0x52> |
| 256: b3 c0 rjmp .+358 ; 0x3be <__vector_16+0x1b8> |
| 258: 23 c0 rjmp .+70 ; 0x2a0 <__vector_16+0x9a> |
| 25a: 14 30 cpi r17, 0x04 ; 4 |
| 25c: 09 f4 brne .+2 ; 0x260 <__vector_16+0x5a> |
| 25e: 79 c0 rjmp .+242 ; 0x352 <__vector_16+0x14c> |
| 260: 14 30 cpi r17, 0x04 ; 4 |
| 262: 08 f4 brcc .+2 ; 0x266 <__vector_16+0x60> |
| 264: 5d c0 rjmp .+186 ; 0x320 <__vector_16+0x11a> |
| 266: 15 30 cpi r17, 0x05 ; 5 |
| 268: 09 f0 breq .+2 ; 0x26c <__vector_16+0x66> |
| 26a: a9 c0 rjmp .+338 ; 0x3be <__vector_16+0x1b8> |
| 26c: 8a c0 rjmp .+276 ; 0x382 <__vector_16+0x17c> |
| 26e: 81 ea ldi r24, 0xA1 ; 161 |
| 270: 8f bd out 0x2f, r24 ; 47 |
| 272: 81 e6 ldi r24, 0x61 ; 97 |
| 274: 85 bd out 0x25, r24 ; 37 |
| 276: 88 e0 ldi r24, 0x08 ; 8 |
| 278: 87 bb out 0x17, r24 ; 23 |
| 27a: 00 23 and r16, r16 |
| 27c: 61 f0 breq .+24 ; 0x296 <__vector_16+0x90> |
| 27e: 82 b3 in r24, 0x12 ; 18 |
| 280: 87 7e andi r24, 0xE7 ; 231 |
| 282: 82 bb out 0x12, r24 ; 18 |
| 284: 95 9a sbi 0x12, 5 ; 18 |
| 286: 80 91 66 00 lds r24, 0x0066 |
| 28a: 81 11 cpse r24, r1 |
| 28c: ed de rcall .-550 ; 0x68 <AdConvert> |
| 28e: 40 98 cbi 0x08, 0 ; 8 |
| 290: 81 e0 ldi r24, 0x01 ; 1 |
| 292: 87 b9 out 0x07, r24 ; 7 |
| 294: 19 c0 rjmp .+50 ; 0x2c8 <__vector_16+0xc2> |
| 296: 82 b3 in r24, 0x12 ; 18 |
| 298: 87 7d andi r24, 0xD7 ; 215 |
| 29a: 82 bb out 0x12, r24 ; 18 |
| 29c: 94 9a sbi 0x12, 4 ; 18 |
| 29e: 8f c0 rjmp .+286 ; 0x3be <__vector_16+0x1b8> |
| 2a0: 82 b3 in r24, 0x12 ; 18 |
| 2a2: 87 7e andi r24, 0xE7 ; 231 |
| 2a4: 82 bb out 0x12, r24 ; 18 |
| 2a6: 95 9a sbi 0x12, 5 ; 18 |
| 2a8: 00 23 and r16, r16 |
| 2aa: e9 f4 brne .+58 ; 0x2e6 <__vector_16+0xe0> |
| 2ac: 81 ea ldi r24, 0xA1 ; 161 |
| 2ae: 8f bd out 0x2f, r24 ; 47 |
| 2b0: 81 e6 ldi r24, 0x61 ; 97 |
| 2b2: 85 bd out 0x25, r24 ; 37 |
| 2b4: 84 e0 ldi r24, 0x04 ; 4 |
| 2b6: 87 bb out 0x17, r24 ; 23 |
| 2b8: 80 91 66 00 lds r24, 0x0066 |
| 2bc: 81 11 cpse r24, r1 |
| 2be: d4 de rcall .-600 ; 0x68 <AdConvert> |
| 2c0: 17 b8 out 0x07, r1 ; 7 |
| 2c2: 88 b1 in r24, 0x08 ; 8 |
| 2c4: 83 60 ori r24, 0x03 ; 3 |
| 2c6: 88 b9 out 0x08, r24 ; 8 |
| 2c8: 80 91 76 00 lds r24, 0x0076 |
| 2cc: 8f 5f subi r24, 0xFF ; 255 |
| 2ce: 80 93 76 00 sts 0x0076, r24 |
| 2d2: 80 91 8a 00 lds r24, 0x008A |
| 2d6: 90 91 8b 00 lds r25, 0x008B |
| 2da: 01 96 adiw r24, 0x01 ; 1 |
| 2dc: 90 93 8b 00 sts 0x008B, r25 |
| 2e0: 80 93 8a 00 sts 0x008A, r24 |
| 2e4: 6c c0 rjmp .+216 ; 0x3be <__vector_16+0x1b8> |
| 2e6: 81 ea ldi r24, 0xA1 ; 161 |
| 2e8: 8f bd out 0x2f, r24 ; 47 |
| 2ea: 81 e6 ldi r24, 0x61 ; 97 |
| 2ec: 85 bd out 0x25, r24 ; 37 |
| 2ee: 88 e0 ldi r24, 0x08 ; 8 |
| 2f0: 65 c0 rjmp .+202 ; 0x3bc <__vector_16+0x1b6> |
| 2f2: 81 ea ldi r24, 0xA1 ; 161 |
| 2f4: 8f bd out 0x2f, r24 ; 47 |
| 2f6: 81 e6 ldi r24, 0x61 ; 97 |
| 2f8: 85 bd out 0x25, r24 ; 37 |
| 2fa: 84 e0 ldi r24, 0x04 ; 4 |
| 2fc: 87 bb out 0x17, r24 ; 23 |
| 2fe: 00 23 and r16, r16 |
| 300: 51 f0 breq .+20 ; 0x316 <__vector_16+0x110> |
| 302: 82 b3 in r24, 0x12 ; 18 |
| 304: 8f 7c andi r24, 0xCF ; 207 |
| 306: 82 bb out 0x12, r24 ; 18 |
| 308: 93 9a sbi 0x12, 3 ; 18 |
| 30a: 80 91 66 00 lds r24, 0x0066 |
| 30e: 81 11 cpse r24, r1 |
| 310: ab de rcall .-682 ; 0x68 <AdConvert> |
| 312: 17 b9 out 0x07, r17 ; 7 |
| 314: 2f c0 rjmp .+94 ; 0x374 <__vector_16+0x16e> |
| 316: 82 b3 in r24, 0x12 ; 18 |
| 318: 87 7e andi r24, 0xE7 ; 231 |
| 31a: 82 bb out 0x12, r24 ; 18 |
| 31c: 95 9a sbi 0x12, 5 ; 18 |
| 31e: 4f c0 rjmp .+158 ; 0x3be <__vector_16+0x1b8> |
| 320: 82 b3 in r24, 0x12 ; 18 |
| 322: 8f 7c andi r24, 0xCF ; 207 |
| 324: 82 bb out 0x12, r24 ; 18 |
| 326: 93 9a sbi 0x12, 3 ; 18 |
| 328: 00 23 and r16, r16 |
| 32a: 69 f4 brne .+26 ; 0x346 <__vector_16+0x140> |
| 32c: 81 ea ldi r24, 0xA1 ; 161 |
| 32e: 8f bd out 0x2f, r24 ; 47 |
| 330: 81 e6 ldi r24, 0x61 ; 97 |
| 332: 85 bd out 0x25, r24 ; 37 |
| 334: 82 e0 ldi r24, 0x02 ; 2 |
| 336: 87 bb out 0x17, r24 ; 23 |
| 338: 80 91 66 00 lds r24, 0x0066 |
| 33c: 81 11 cpse r24, r1 |
| 33e: 94 de rcall .-728 ; 0x68 <AdConvert> |
| 340: 81 e0 ldi r24, 0x01 ; 1 |
| 342: 87 b9 out 0x07, r24 ; 7 |
| 344: be cf rjmp .-132 ; 0x2c2 <__vector_16+0xbc> |
| 346: 81 ea ldi r24, 0xA1 ; 161 |
| 348: 8f bd out 0x2f, r24 ; 47 |
| 34a: 81 e6 ldi r24, 0x61 ; 97 |
| 34c: 85 bd out 0x25, r24 ; 37 |
| 34e: 84 e0 ldi r24, 0x04 ; 4 |
| 350: 35 c0 rjmp .+106 ; 0x3bc <__vector_16+0x1b6> |
| 352: 81 ea ldi r24, 0xA1 ; 161 |
| 354: 8f bd out 0x2f, r24 ; 47 |
| 356: 81 e6 ldi r24, 0x61 ; 97 |
| 358: 85 bd out 0x25, r24 ; 37 |
| 35a: 82 e0 ldi r24, 0x02 ; 2 |
| 35c: 87 bb out 0x17, r24 ; 23 |
| 35e: 00 23 and r16, r16 |
| 360: 59 f0 breq .+22 ; 0x378 <__vector_16+0x172> |
| 362: 82 b3 in r24, 0x12 ; 18 |
| 364: 87 7d andi r24, 0xD7 ; 215 |
| 366: 82 bb out 0x12, r24 ; 18 |
| 368: 94 9a sbi 0x12, 4 ; 18 |
| 36a: 80 91 66 00 lds r24, 0x0066 |
| 36e: 81 11 cpse r24, r1 |
| 370: 7b de rcall .-778 ; 0x68 <AdConvert> |
| 372: 17 b8 out 0x07, r1 ; 7 |
| 374: 40 98 cbi 0x08, 0 ; 8 |
| 376: a8 cf rjmp .-176 ; 0x2c8 <__vector_16+0xc2> |
| 378: 82 b3 in r24, 0x12 ; 18 |
| 37a: 8f 7c andi r24, 0xCF ; 207 |
| 37c: 82 bb out 0x12, r24 ; 18 |
| 37e: 93 9a sbi 0x12, 3 ; 18 |
| 380: 1e c0 rjmp .+60 ; 0x3be <__vector_16+0x1b8> |
| 382: 82 b3 in r24, 0x12 ; 18 |
| 384: 87 7d andi r24, 0xD7 ; 215 |
| 386: 82 bb out 0x12, r24 ; 18 |
| 388: 94 9a sbi 0x12, 4 ; 18 |
| 38a: 00 23 and r16, r16 |
| 38c: 91 f4 brne .+36 ; 0x3b2 <__vector_16+0x1ac> |
| 38e: 81 ea ldi r24, 0xA1 ; 161 |
| 390: 8f bd out 0x2f, r24 ; 47 |
| 392: 81 e6 ldi r24, 0x61 ; 97 |
| 394: 85 bd out 0x25, r24 ; 37 |
| 396: 88 e0 ldi r24, 0x08 ; 8 |
| 398: 87 bb out 0x17, r24 ; 23 |
| 39a: 80 91 66 00 lds r24, 0x0066 |
| 39e: 81 11 cpse r24, r1 |
| 3a0: 63 de rcall .-826 ; 0x68 <AdConvert> |
| 3a2: 82 e0 ldi r24, 0x02 ; 2 |
| 3a4: 87 b9 out 0x07, r24 ; 7 |
| 3a6: 88 b1 in r24, 0x08 ; 8 |
| 3a8: 83 60 ori r24, 0x03 ; 3 |
| 3aa: 88 b9 out 0x08, r24 ; 8 |
| 3ac: 10 92 76 00 sts 0x0076, r1 |
| 3b0: 90 cf rjmp .-224 ; 0x2d2 <__vector_16+0xcc> |
| 3b2: 81 ea ldi r24, 0xA1 ; 161 |
| 3b4: 8f bd out 0x2f, r24 ; 47 |
| 3b6: 81 e6 ldi r24, 0x61 ; 97 |
| 3b8: 85 bd out 0x25, r24 ; 37 |
| 3ba: 82 e0 ldi r24, 0x02 ; 2 |
| 3bc: 87 bb out 0x17, r24 ; 23 |
| 3be: 45 99 sbic 0x08, 5 ; 8 |
| 3c0: 03 c0 rjmp .+6 ; 0x3c8 <__vector_16+0x1c2> |
| 3c2: 00 23 and r16, r16 |
| 3c4: 09 f0 breq .+2 ; 0x3c8 <__vector_16+0x1c2> |
| 3c6: 32 cf rjmp .-412 ; 0x22c <__vector_16+0x26> |
| 3c8: 45 9b sbis 0x08, 5 ; 8 |
| 3ca: 03 c0 rjmp .+6 ; 0x3d2 <__vector_16+0x1cc> |
| 3cc: 00 23 and r16, r16 |
| 3ce: 09 f4 brne .+2 ; 0x3d2 <__vector_16+0x1cc> |
| 3d0: 2d cf rjmp .-422 ; 0x22c <__vector_16+0x26> |
| 3d2: 10 92 66 00 sts 0x0066, r1 |
| 3d6: ff 91 pop r31 |
| 3d8: ef 91 pop r30 |
| 3da: bf 91 pop r27 |
| 3dc: af 91 pop r26 |
| 3de: 9f 91 pop r25 |
| 3e0: 8f 91 pop r24 |
| 3e2: 7f 91 pop r23 |
| 3e4: 6f 91 pop r22 |
| 3e6: 5f 91 pop r21 |
| 3e8: 4f 91 pop r20 |
| 3ea: 3f 91 pop r19 |
| 3ec: 2f 91 pop r18 |
| 3ee: 1f 91 pop r17 |
| 3f0: 0f 91 pop r16 |
| 3f2: 0f 90 pop r0 |
| 3f4: 0f be out 0x3f, r0 ; 63 |
| 3f6: 0f 90 pop r0 |
| 3f8: 1f 90 pop r1 |
| 3fa: 18 95 reti |
| |
| 000003fc <SetPWM>: |
| 3fc: 20 91 79 00 lds r18, 0x0079 |
| 400: 80 91 65 00 lds r24, 0x0065 |
| 404: 82 17 cp r24, r18 |
| 406: 10 f4 brcc .+4 ; 0x40c <SetPWM+0x10> |
| 408: ab 9a sbi 0x15, 3 ; 21 |
| 40a: 28 2f mov r18, r24 |
| 40c: 80 91 7b 00 lds r24, 0x007B |
| 410: 90 91 7c 00 lds r25, 0x007C |
| 414: 89 3c cpi r24, 0xC9 ; 201 |
| 416: 91 05 cpc r25, r1 |
| 418: 60 f0 brcs .+24 ; 0x432 <SetPWM+0x36> |
| 41a: 1b bc out 0x2b, r1 ; 43 |
| 41c: 1a bc out 0x2a, r1 ; 42 |
| 41e: 19 bc out 0x29, r1 ; 41 |
| 420: 18 bc out 0x28, r1 ; 40 |
| 422: 13 bc out 0x23, r1 ; 35 |
| 424: ab 9a sbi 0x15, 3 ; 21 |
| 426: 01 97 sbiw r24, 0x01 ; 1 |
| 428: 90 93 7c 00 sts 0x007C, r25 |
| 42c: 80 93 7b 00 sts 0x007B, r24 |
| 430: 08 95 ret |
| 432: 82 2f mov r24, r18 |
| 434: 99 27 eor r25, r25 |
| 436: 9b bd out 0x2b, r25 ; 43 |
| 438: 8a bd out 0x2a, r24 ; 42 |
| 43a: 99 bd out 0x29, r25 ; 41 |
| 43c: 88 bd out 0x28, r24 ; 40 |
| 43e: 23 bd out 0x23, r18 ; 35 |
| 440: 08 95 ret |
| |
| 00000442 <PWM_Init>: |
| 442: 91 e0 ldi r25, 0x01 ; 1 |
| 444: 9f bd out 0x2f, r25 ; 47 |
| 446: 81 e4 ldi r24, 0x41 ; 65 |
| 448: 85 bd out 0x25, r24 ; 37 |
| 44a: 8e e0 ldi r24, 0x0E ; 14 |
| 44c: 87 bb out 0x17, r24 ; 23 |
| 44e: 88 b3 in r24, 0x18 ; 24 |
| 450: 81 7f andi r24, 0xF1 ; 241 |
| 452: 88 bb out 0x18, r24 ; 24 |
| 454: 9e bd out 0x2e, r25 ; 46 |
| 456: 08 95 ret |
| |
| 00000458 <Wait>: |
| 458: 92 b7 in r25, 0x32 ; 50 |
| 45a: 98 0f add r25, r24 |
| 45c: 29 2f mov r18, r25 |
| 45e: 33 27 eor r19, r19 |
| 460: 82 b7 in r24, 0x32 ; 50 |
| 462: 82 1b sub r24, r18 |
| 464: 87 fd sbrc r24, 7 |
| 466: fc cf rjmp .-8 ; 0x460 <__stack+0x1> |
| 468: 08 95 ret |
| |
| 0000046a <Delay>: |
| 46a: 80 e0 ldi r24, 0x00 ; 0 |
| 46c: 90 e0 ldi r25, 0x00 ; 0 |
| 46e: 08 95 ret |
| |
| 00000470 <SollwertErmittlung>: |
| 470: 80 91 81 00 lds r24, 0x0081 |
| 474: 90 91 82 00 lds r25, 0x0082 |
| 478: 89 2b or r24, r25 |
| 47a: 09 f0 breq .+2 ; 0x47e <SollwertErmittlung+0xe> |
| 47c: 59 c0 rjmp .+178 ; 0x530 <SollwertErmittlung+0xc0> |
| 47e: 80 91 83 00 lds r24, 0x0083 |
| 482: 90 91 84 00 lds r25, 0x0084 |
| 486: 89 2b or r24, r25 |
| 488: 99 f0 breq .+38 ; 0x4b0 <SollwertErmittlung+0x40> |
| 48a: 90 91 9d 00 lds r25, 0x009D |
| 48e: 8f ef ldi r24, 0xFF ; 255 |
| 490: 98 9f mul r25, r24 |
| 492: c0 01 movw r24, r0 |
| 494: 11 24 eor r1, r1 |
| 496: 68 ec ldi r22, 0xC8 ; 200 |
| 498: 70 e0 ldi r23, 0x00 ; 0 |
| 49a: 58 da rcall .-2896 ; 0xfffff94c <__eeprom_end+0xff7ef94c> |
| 49c: 70 93 8f 00 sts 0x008F, r23 |
| 4a0: 60 93 8e 00 sts 0x008E, r22 |
| 4a4: 10 92 68 00 sts 0x0068, r1 |
| 4a8: 89 b7 in r24, 0x39 ; 57 |
| 4aa: 8f 7d andi r24, 0xDF ; 223 |
| 4ac: 89 bf out 0x39, r24 ; 57 |
| 4ae: 31 c0 rjmp .+98 ; 0x512 <SollwertErmittlung+0xa2> |
| 4b0: 80 91 94 00 lds r24, 0x0094 |
| 4b4: 85 31 cpi r24, 0x15 ; 21 |
| 4b6: 78 f1 brcs .+94 ; 0x516 <SollwertErmittlung+0xa6> |
| 4b8: 81 e0 ldi r24, 0x01 ; 1 |
| 4ba: 80 93 68 00 sts 0x0068, r24 |
| 4be: 20 91 90 00 lds r18, 0x0090 |
| 4c2: 30 91 91 00 lds r19, 0x0091 |
| 4c6: 41 e0 ldi r20, 0x01 ; 1 |
| 4c8: 2d 32 cpi r18, 0x2D ; 45 |
| 4ca: 34 07 cpc r19, r20 |
| 4cc: 30 f4 brcc .+12 ; 0x4da <SollwertErmittlung+0x6a> |
| 4ce: 29 3c cpi r18, 0xC9 ; 201 |
| 4d0: 31 05 cpc r19, r1 |
| 4d2: 40 f4 brcc .+16 ; 0x4e4 <SollwertErmittlung+0x74> |
| 4d4: 2b 30 cpi r18, 0x0B ; 11 |
| 4d6: 31 05 cpc r19, r1 |
| 4d8: 38 f4 brcc .+14 ; 0x4e8 <SollwertErmittlung+0x78> |
| 4da: 10 92 8f 00 sts 0x008F, r1 |
| 4de: 10 92 8e 00 sts 0x008E, r1 |
| 4e2: 17 c0 rjmp .+46 ; 0x512 <SollwertErmittlung+0xa2> |
| 4e4: 28 ec ldi r18, 0xC8 ; 200 |
| 4e6: 30 e0 ldi r19, 0x00 ; 0 |
| 4e8: 8c ef ldi r24, 0xFC ; 252 |
| 4ea: 90 e0 ldi r25, 0x00 ; 0 |
| 4ec: ac 01 movw r20, r24 |
| 4ee: 24 9f mul r18, r20 |
| 4f0: c0 01 movw r24, r0 |
| 4f2: 25 9f mul r18, r21 |
| 4f4: 90 0d add r25, r0 |
| 4f6: 34 9f mul r19, r20 |
| 4f8: 90 0d add r25, r0 |
| 4fa: 11 24 eor r1, r1 |
| 4fc: 88 5d subi r24, 0xD8 ; 216 |
| 4fe: 99 40 sbci r25, 0x09 ; 9 |
| 500: 64 eb ldi r22, 0xB4 ; 180 |
| 502: 70 e0 ldi r23, 0x00 ; 0 |
| 504: 23 da rcall .-3002 ; 0xfffff94c <__eeprom_end+0xff7ef94c> |
| 506: 6d 5f subi r22, 0xFD ; 253 |
| 508: 7f 4f sbci r23, 0xFF ; 255 |
| 50a: 70 93 8f 00 sts 0x008F, r23 |
| 50e: 60 93 8e 00 sts 0x008E, r22 |
| 512: ab 98 cbi 0x15, 3 ; 21 |
| 514: 1a c0 rjmp .+52 ; 0x54a <SollwertErmittlung+0xda> |
| 516: 80 91 8e 00 lds r24, 0x008E |
| 51a: 90 91 8f 00 lds r25, 0x008F |
| 51e: 00 97 sbiw r24, 0x00 ; 0 |
| 520: 29 f0 breq .+10 ; 0x52c <SollwertErmittlung+0xbc> |
| 522: 01 97 sbiw r24, 0x01 ; 1 |
| 524: 90 93 8f 00 sts 0x008F, r25 |
| 528: 80 93 8e 00 sts 0x008E, r24 |
| 52c: ab 9a sbi 0x15, 3 ; 21 |
| 52e: 0d c0 rjmp .+26 ; 0x54a <SollwertErmittlung+0xda> |
| 530: 80 91 b0 02 lds r24, 0x02B0 |
| 534: 99 27 eor r25, r25 |
| 536: 90 93 8f 00 sts 0x008F, r25 |
| 53a: 80 93 8e 00 sts 0x008E, r24 |
| 53e: 10 92 68 00 sts 0x0068, r1 |
| 542: ab 98 cbi 0x15, 3 ; 21 |
| 544: 89 b7 in r24, 0x39 ; 57 |
| 546: 8f 7d andi r24, 0xDF ; 223 |
| 548: 89 bf out 0x39, r24 ; 57 |
| 54a: 80 91 8e 00 lds r24, 0x008E |
| 54e: 90 91 8f 00 lds r25, 0x008F |
| 552: 8f 3f cpi r24, 0xFF ; 255 |
| 554: 91 05 cpc r25, r1 |
| 556: 39 f0 breq .+14 ; 0x566 <SollwertErmittlung+0xf6> |
| 558: 30 f0 brcs .+12 ; 0x566 <SollwertErmittlung+0xf6> |
| 55a: 8f ef ldi r24, 0xFF ; 255 |
| 55c: 90 e0 ldi r25, 0x00 ; 0 |
| 55e: 90 93 8f 00 sts 0x008F, r25 |
| 562: 80 93 8e 00 sts 0x008E, r24 |
| 566: 80 91 8e 00 lds r24, 0x008E |
| 56a: 99 27 eor r25, r25 |
| 56c: 08 95 ret |
| |
| 0000056e <DebugAusgaben>: |
| 56e: 80 91 7b 00 lds r24, 0x007B |
| 572: 90 91 7c 00 lds r25, 0x007C |
| 576: 90 93 8f 03 sts 0x038F, r25 |
| 57a: 80 93 8e 03 sts 0x038E, r24 |
| 57e: 80 91 7e 00 lds r24, 0x007E |
| 582: 99 27 eor r25, r25 |
| 584: 90 93 91 03 sts 0x0391, r25 |
| 588: 80 93 90 03 sts 0x0390, r24 |
| 58c: 80 91 8c 00 lds r24, 0x008C |
| 590: 90 91 8d 00 lds r25, 0x008D |
| 594: 90 93 93 03 sts 0x0393, r25 |
| 598: 80 93 92 03 sts 0x0392, r24 |
| 59c: 80 91 90 00 lds r24, 0x0090 |
| 5a0: 90 91 91 00 lds r25, 0x0091 |
| 5a4: 90 93 95 03 sts 0x0395, r25 |
| 5a8: 80 93 94 03 sts 0x0394, r24 |
| 5ac: 08 95 ret |
| |
| 000005ae <RotBlink>: |
| 5ae: 1f 93 push r17 |
| 5b0: 18 2f mov r17, r24 |
| 5b2: 78 94 sei |
| 5b4: 08 c0 rjmp .+16 ; 0x5c6 <RotBlink+0x18> |
| 5b6: ab 9a sbi 0x15, 3 ; 21 |
| 5b8: 8c e2 ldi r24, 0x2C ; 44 |
| 5ba: 91 e0 ldi r25, 0x01 ; 1 |
| 5bc: 8a d5 rcall .+2836 ; 0x10d2 <Delay_ms> |
| 5be: ab 98 cbi 0x15, 3 ; 21 |
| 5c0: 8c e2 ldi r24, 0x2C ; 44 |
| 5c2: 91 e0 ldi r25, 0x01 ; 1 |
| 5c4: 86 d5 rcall .+2828 ; 0x10d2 <Delay_ms> |
| 5c6: 11 50 subi r17, 0x01 ; 1 |
| 5c8: b0 f7 brcc .-20 ; 0x5b6 <RotBlink+0x8> |
| 5ca: 88 ee ldi r24, 0xE8 ; 232 |
| 5cc: 93 e0 ldi r25, 0x03 ; 3 |
| 5ce: 81 d5 rcall .+2818 ; 0x10d2 <Delay_ms> |
| 5d0: 1f 91 pop r17 |
| 5d2: 08 95 ret |
| |
| 000005d4 <DelayM>: |
| 5d4: cf 93 push r28 |
| 5d6: df 93 push r29 |
| 5d8: ec 01 movw r28, r24 |
| 5da: 17 c0 rjmp .+46 ; 0x60a <DelayM+0x36> |
| 5dc: 8b dd rcall .-1258 ; 0xf4 <FastADConvert> |
| 5de: 80 91 ad 02 lds r24, 0x02AD |
| 5e2: 90 91 ae 02 lds r25, 0x02AE |
| 5e6: 88 58 subi r24, 0x88 ; 136 |
| 5e8: 9f 4f sbci r25, 0xFF ; 255 |
| 5ea: 20 91 7b 00 lds r18, 0x007B |
| 5ee: 30 91 7c 00 lds r19, 0x007C |
| 5f2: 82 17 cp r24, r18 |
| 5f4: 93 07 cpc r25, r19 |
| 5f6: 48 f4 brcc .+18 ; 0x60a <DelayM+0x36> |
| 5f8: 82 b3 in r24, 0x12 ; 18 |
| 5fa: 87 7c andi r24, 0xC7 ; 199 |
| 5fc: 82 bb out 0x12, r24 ; 18 |
| 5fe: 88 b3 in r24, 0x18 ; 24 |
| 600: 81 7f andi r24, 0xF1 ; 241 |
| 602: 88 bb out 0x18, r24 ; 24 |
| 604: 81 e0 ldi r24, 0x01 ; 1 |
| 606: 90 e0 ldi r25, 0x00 ; 0 |
| 608: 07 c0 rjmp .+14 ; 0x618 <DelayM+0x44> |
| 60a: 21 97 sbiw r28, 0x01 ; 1 |
| 60c: 8f ef ldi r24, 0xFF ; 255 |
| 60e: cf 3f cpi r28, 0xFF ; 255 |
| 610: d8 07 cpc r29, r24 |
| 612: 21 f7 brne .-56 ; 0x5dc <DelayM+0x8> |
| 614: 80 e0 ldi r24, 0x00 ; 0 |
| 616: 90 e0 ldi r25, 0x00 ; 0 |
| 618: df 91 pop r29 |
| 61a: cf 91 pop r28 |
| 61c: 08 95 ret |
| |
| 0000061e <MotorTon>: |
| 61e: 8f 92 push r8 |
| 620: 9f 92 push r9 |
| 622: bf 92 push r11 |
| 624: cf 92 push r12 |
| 626: df 92 push r13 |
| 628: ef 92 push r14 |
| 62a: ff 92 push r15 |
| 62c: 0f 93 push r16 |
| 62e: 1f 93 push r17 |
| 630: cf 93 push r28 |
| 632: df 93 push r29 |
| 634: cd b7 in r28, 0x3d ; 61 |
| 636: de b7 in r29, 0x3e ; 62 |
| 638: 25 97 sbiw r28, 0x05 ; 5 |
| 63a: 0f b6 in r0, 0x3f ; 63 |
| 63c: f8 94 cli |
| 63e: de bf out 0x3e, r29 ; 62 |
| 640: 0f be out 0x3f, r0 ; 63 |
| 642: cd bf out 0x3d, r28 ; 61 |
| 644: de 01 movw r26, r28 |
| 646: 11 96 adiw r26, 0x01 ; 1 |
| 648: e9 e6 ldi r30, 0x69 ; 105 |
| 64a: f0 e0 ldi r31, 0x00 ; 0 |
| 64c: 85 e0 ldi r24, 0x05 ; 5 |
| 64e: 01 90 ld r0, Z+ |
| 650: 0d 92 st X+, r0 |
| 652: 81 50 subi r24, 0x01 ; 1 |
| 654: e1 f7 brne .-8 ; 0x64e <MotorTon+0x30> |
| 656: ab 98 cbi 0x15, 3 ; 21 |
| 658: 80 91 67 00 lds r24, 0x0067 |
| 65c: fe 01 movw r30, r28 |
| 65e: e8 0f add r30, r24 |
| 660: f1 1d adc r31, r1 |
| 662: 81 81 ldd r24, Z+1 ; 0x01 |
| 664: 99 27 eor r25, r25 |
| 666: 2c e2 ldi r18, 0x2C ; 44 |
| 668: 31 e0 ldi r19, 0x01 ; 1 |
| 66a: ac 01 movw r20, r24 |
| 66c: 42 9f mul r20, r18 |
| 66e: c0 01 movw r24, r0 |
| 670: 43 9f mul r20, r19 |
| 672: 90 0d add r25, r0 |
| 674: 52 9f mul r21, r18 |
| 676: 90 0d add r25, r0 |
| 678: 11 24 eor r1, r1 |
| 67a: 2b d5 rcall .+2646 ; 0x10d2 <Delay_ms> |
| 67c: 10 92 78 00 sts 0x0078, r1 |
| 680: 43 98 cbi 0x08, 3 ; 8 |
| 682: f8 94 cli |
| 684: 8a e0 ldi r24, 0x0A ; 10 |
| 686: b5 d6 rcall .+3434 ; 0x13f2 <uart_putchar> |
| 688: 82 b3 in r24, 0x12 ; 18 |
| 68a: 87 7c andi r24, 0xC7 ; 199 |
| 68c: 82 bb out 0x12, r24 ; 18 |
| 68e: 81 e0 ldi r24, 0x01 ; 1 |
| 690: 8f bd out 0x2f, r24 ; 47 |
| 692: 81 e4 ldi r24, 0x41 ; 65 |
| 694: 85 bd out 0x25, r24 ; 37 |
| 696: 8e e0 ldi r24, 0x0E ; 14 |
| 698: 87 bb out 0x17, r24 ; 23 |
| 69a: 88 b3 in r24, 0x18 ; 24 |
| 69c: 81 7f andi r24, 0xF1 ; 241 |
| 69e: 88 bb out 0x18, r24 ; 24 |
| 6a0: 10 92 7d 00 sts 0x007D, r1 |
| 6a4: 82 e3 ldi r24, 0x32 ; 50 |
| 6a6: 90 e0 ldi r25, 0x00 ; 0 |
| 6a8: 95 df rcall .-214 ; 0x5d4 <DelayM> |
| 6aa: 80 91 7d 00 lds r24, 0x007D |
| 6ae: 99 27 eor r25, r25 |
| 6b0: 90 93 ae 02 sts 0x02AE, r25 |
| 6b4: 80 93 ad 02 sts 0x02AD, r24 |
| 6b8: 10 92 7c 00 sts 0x007C, r1 |
| 6bc: 10 92 7b 00 sts 0x007B, r1 |
| 6c0: 94 9a sbi 0x12, 4 ; 18 |
| 6c2: c3 9a sbi 0x18, 3 ; 24 |
| 6c4: 83 e0 ldi r24, 0x03 ; 3 |
| 6c6: 90 e0 ldi r25, 0x00 ; 0 |
| 6c8: 85 df rcall .-246 ; 0x5d4 <DelayM> |
| 6ca: 88 23 and r24, r24 |
| 6cc: 11 f4 brne .+4 ; 0x6d2 <MotorTon+0xb4> |
| 6ce: bb 24 eor r11, r11 |
| 6d0: 04 c0 rjmp .+8 ; 0x6da <MotorTon+0xbc> |
| 6d2: 81 e3 ldi r24, 0x31 ; 49 |
| 6d4: 8e d6 rcall .+3356 ; 0x13f2 <uart_putchar> |
| 6d6: bb 24 eor r11, r11 |
| 6d8: b3 94 inc r11 |
| 6da: 82 b3 in r24, 0x12 ; 18 |
| 6dc: 87 7c andi r24, 0xC7 ; 199 |
| 6de: 82 bb out 0x12, r24 ; 18 |
| 6e0: 88 b3 in r24, 0x18 ; 24 |
| 6e2: 81 7f andi r24, 0xF1 ; 241 |
| 6e4: 88 bb out 0x18, r24 ; 24 |
| 6e6: 10 92 7c 00 sts 0x007C, r1 |
| 6ea: 10 92 7b 00 sts 0x007B, r1 |
| 6ee: 93 9a sbi 0x12, 3 ; 18 |
| 6f0: c2 9a sbi 0x18, 2 ; 24 |
| 6f2: 83 e0 ldi r24, 0x03 ; 3 |
| 6f4: 90 e0 ldi r25, 0x00 ; 0 |
| 6f6: 6e df rcall .-292 ; 0x5d4 <DelayM> |
| 6f8: 88 23 and r24, r24 |
| 6fa: 21 f0 breq .+8 ; 0x704 <MotorTon+0xe6> |
| 6fc: 82 e3 ldi r24, 0x32 ; 50 |
| 6fe: 79 d6 rcall .+3314 ; 0x13f2 <uart_putchar> |
| 700: b2 e0 ldi r27, 0x02 ; 2 |
| 702: bb 2e mov r11, r27 |
| 704: 82 b3 in r24, 0x12 ; 18 |
| 706: 87 7c andi r24, 0xC7 ; 199 |
| 708: 82 bb out 0x12, r24 ; 18 |
| 70a: 88 b3 in r24, 0x18 ; 24 |
| 70c: 81 7f andi r24, 0xF1 ; 241 |
| 70e: 88 bb out 0x18, r24 ; 24 |
| 710: 10 92 7c 00 sts 0x007C, r1 |
| 714: 10 92 7b 00 sts 0x007B, r1 |
| 718: 94 9a sbi 0x12, 4 ; 18 |
| 71a: c1 9a sbi 0x18, 1 ; 24 |
| 71c: 83 e0 ldi r24, 0x03 ; 3 |
| 71e: 90 e0 ldi r25, 0x00 ; 0 |
| 720: 59 df rcall .-334 ; 0x5d4 <DelayM> |
| 722: 88 23 and r24, r24 |
| 724: 21 f0 breq .+8 ; 0x72e <MotorTon+0x110> |
| 726: 83 e3 ldi r24, 0x33 ; 51 |
| 728: 64 d6 rcall .+3272 ; 0x13f2 <uart_putchar> |
| 72a: a3 e0 ldi r26, 0x03 ; 3 |
| 72c: ba 2e mov r11, r26 |
| 72e: 82 b3 in r24, 0x12 ; 18 |
| 730: 87 7c andi r24, 0xC7 ; 199 |
| 732: 82 bb out 0x12, r24 ; 18 |
| 734: 88 b3 in r24, 0x18 ; 24 |
| 736: 81 7f andi r24, 0xF1 ; 241 |
| 738: 88 bb out 0x18, r24 ; 24 |
| 73a: 93 9a sbi 0x12, 3 ; 18 |
| 73c: c1 9a sbi 0x18, 1 ; 24 |
| 73e: 83 e0 ldi r24, 0x03 ; 3 |
| 740: 90 e0 ldi r25, 0x00 ; 0 |
| 742: 48 df rcall .-368 ; 0x5d4 <DelayM> |
| 744: 88 23 and r24, r24 |
| 746: 21 f0 breq .+8 ; 0x750 <MotorTon+0x132> |
| 748: 87 e3 ldi r24, 0x37 ; 55 |
| 74a: 53 d6 rcall .+3238 ; 0x13f2 <uart_putchar> |
| 74c: f3 e0 ldi r31, 0x03 ; 3 |
| 74e: bf 2e mov r11, r31 |
| 750: 82 b3 in r24, 0x12 ; 18 |
| 752: 87 7c andi r24, 0xC7 ; 199 |
| 754: 82 bb out 0x12, r24 ; 18 |
| 756: 88 b3 in r24, 0x18 ; 24 |
| 758: 81 7f andi r24, 0xF1 ; 241 |
| 75a: 88 bb out 0x18, r24 ; 24 |
| 75c: 80 e1 ldi r24, 0x10 ; 16 |
| 75e: 97 e2 ldi r25, 0x27 ; 39 |
| 760: 39 df rcall .-398 ; 0x5d4 <DelayM> |
| 762: bb 20 and r11, r11 |
| 764: 19 f0 breq .+6 ; 0x76c <MotorTon+0x14e> |
| 766: 8b 2d mov r24, r11 |
| 768: 22 df rcall .-444 ; 0x5ae <RotBlink> |
| 76a: fd cf rjmp .-6 ; 0x766 <MotorTon+0x148> |
| 76c: 8c b1 in r24, 0x0c ; 12 |
| 76e: 80 32 cpi r24, 0x20 ; 32 |
| 770: 31 f0 breq .+12 ; 0x77e <MotorTon+0x160> |
| 772: e8 ee ldi r30, 0xE8 ; 232 |
| 774: 8e 2e mov r8, r30 |
| 776: e3 e0 ldi r30, 0x03 ; 3 |
| 778: 9e 2e mov r9, r30 |
| 77a: 82 e3 ldi r24, 0x32 ; 50 |
| 77c: 06 c0 rjmp .+12 ; 0x78a <MotorTon+0x16c> |
| 77e: 8f e5 ldi r24, 0x5F ; 95 |
| 780: 38 d6 rcall .+3184 ; 0x13f2 <uart_putchar> |
| 782: 88 24 eor r8, r8 |
| 784: 8a 94 dec r8 |
| 786: 98 2c mov r9, r8 |
| 788: 88 e2 ldi r24, 0x28 ; 40 |
| 78a: 10 92 7c 00 sts 0x007C, r1 |
| 78e: 10 92 7b 00 sts 0x007B, r1 |
| 792: 00 e0 ldi r16, 0x00 ; 0 |
| 794: 10 e0 ldi r17, 0x00 ; 0 |
| 796: c8 2e mov r12, r24 |
| 798: dd 24 eor r13, r13 |
| 79a: 93 9a sbi 0x12, 3 ; 18 |
| 79c: 81 e0 ldi r24, 0x01 ; 1 |
| 79e: 90 e0 ldi r25, 0x00 ; 0 |
| 7a0: 19 df rcall .-462 ; 0x5d4 <DelayM> |
| 7a2: 82 b3 in r24, 0x12 ; 18 |
| 7a4: 87 7c andi r24, 0xC7 ; 199 |
| 7a6: 82 bb out 0x12, r24 ; 18 |
| 7a8: 88 b3 in r24, 0x18 ; 24 |
| 7aa: 81 7f andi r24, 0xF1 ; 241 |
| 7ac: 88 bb out 0x18, r24 ; 24 |
| 7ae: c3 9a sbi 0x18, 3 ; 24 |
| 7b0: 81 e0 ldi r24, 0x01 ; 1 |
| 7b2: 90 e0 ldi r25, 0x00 ; 0 |
| 7b4: 0f df rcall .-482 ; 0x5d4 <DelayM> |
| 7b6: 82 b3 in r24, 0x12 ; 18 |
| 7b8: 87 7c andi r24, 0xC7 ; 199 |
| 7ba: 82 bb out 0x12, r24 ; 18 |
| 7bc: 88 b3 in r24, 0x18 ; 24 |
| 7be: 81 7f andi r24, 0xF1 ; 241 |
| 7c0: 88 bb out 0x18, r24 ; 24 |
| 7c2: 76 01 movw r14, r12 |
| 7c4: 80 91 ad 02 lds r24, 0x02AD |
| 7c8: 90 91 ae 02 lds r25, 0x02AE |
| 7cc: 8c 0d add r24, r12 |
| 7ce: 9d 1d adc r25, r13 |
| 7d0: 20 91 7b 00 lds r18, 0x007B |
| 7d4: 30 91 7c 00 lds r19, 0x007C |
| 7d8: 82 17 cp r24, r18 |
| 7da: 93 07 cpc r25, r19 |
| 7dc: 28 f4 brcc .+10 ; 0x7e8 <MotorTon+0x1ca> |
| 7de: 84 e3 ldi r24, 0x34 ; 52 |
| 7e0: 08 d6 rcall .+3088 ; 0x13f2 <uart_putchar> |
| 7e2: 74 e0 ldi r23, 0x04 ; 4 |
| 7e4: b7 2e mov r11, r23 |
| 7e6: 05 c0 rjmp .+10 ; 0x7f2 <MotorTon+0x1d4> |
| 7e8: 0f 5f subi r16, 0xFF ; 255 |
| 7ea: 1f 4f sbci r17, 0xFF ; 255 |
| 7ec: 08 15 cp r16, r8 |
| 7ee: 19 05 cpc r17, r9 |
| 7f0: a1 f6 brne .-88 ; 0x79a <MotorTon+0x17c> |
| 7f2: 10 92 7c 00 sts 0x007C, r1 |
| 7f6: 10 92 7b 00 sts 0x007B, r1 |
| 7fa: 00 e0 ldi r16, 0x00 ; 0 |
| 7fc: 10 e0 ldi r17, 0x00 ; 0 |
| 7fe: 94 9a sbi 0x12, 4 ; 18 |
| 800: 81 e0 ldi r24, 0x01 ; 1 |
| 802: 90 e0 ldi r25, 0x00 ; 0 |
| 804: e7 de rcall .-562 ; 0x5d4 <DelayM> |
| 806: 82 b3 in r24, 0x12 ; 18 |
| 808: 87 7c andi r24, 0xC7 ; 199 |
| 80a: 82 bb out 0x12, r24 ; 18 |
| 80c: 88 b3 in r24, 0x18 ; 24 |
| 80e: 81 7f andi r24, 0xF1 ; 241 |
| 810: 88 bb out 0x18, r24 ; 24 |
| 812: c2 9a sbi 0x18, 2 ; 24 |
| 814: 81 e0 ldi r24, 0x01 ; 1 |
| 816: 90 e0 ldi r25, 0x00 ; 0 |
| 818: dd de rcall .-582 ; 0x5d4 <DelayM> |
| 81a: 82 b3 in r24, 0x12 ; 18 |
| 81c: 87 7c andi r24, 0xC7 ; 199 |
| 81e: 82 bb out 0x12, r24 ; 18 |
| 820: 88 b3 in r24, 0x18 ; 24 |
| 822: 81 7f andi r24, 0xF1 ; 241 |
| 824: 88 bb out 0x18, r24 ; 24 |
| 826: 80 91 ad 02 lds r24, 0x02AD |
| 82a: 90 91 ae 02 lds r25, 0x02AE |
| 82e: 8e 0d add r24, r14 |
| 830: 9f 1d adc r25, r15 |
| 832: 20 91 7b 00 lds r18, 0x007B |
| 836: 30 91 7c 00 lds r19, 0x007C |
| 83a: 82 17 cp r24, r18 |
| 83c: 93 07 cpc r25, r19 |
| 83e: 28 f4 brcc .+10 ; 0x84a <MotorTon+0x22c> |
| 840: 85 e3 ldi r24, 0x35 ; 53 |
| 842: d7 d5 rcall .+2990 ; 0x13f2 <uart_putchar> |
| 844: 65 e0 ldi r22, 0x05 ; 5 |
| 846: b6 2e mov r11, r22 |
| 848: 05 c0 rjmp .+10 ; 0x854 <MotorTon+0x236> |
| 84a: 0f 5f subi r16, 0xFF ; 255 |
| 84c: 1f 4f sbci r17, 0xFF ; 255 |
| 84e: 08 15 cp r16, r8 |
| 850: 19 05 cpc r17, r9 |
| 852: a9 f6 brne .-86 ; 0x7fe <MotorTon+0x1e0> |
| 854: 10 92 7c 00 sts 0x007C, r1 |
| 858: 10 92 7b 00 sts 0x007B, r1 |
| 85c: 00 e0 ldi r16, 0x00 ; 0 |
| 85e: 10 e0 ldi r17, 0x00 ; 0 |
| 860: 95 9a sbi 0x12, 5 ; 18 |
| 862: 81 e0 ldi r24, 0x01 ; 1 |
| 864: 90 e0 ldi r25, 0x00 ; 0 |
| 866: b6 de rcall .-660 ; 0x5d4 <DelayM> |
| 868: 82 b3 in r24, 0x12 ; 18 |
| 86a: 87 7c andi r24, 0xC7 ; 199 |
| 86c: 82 bb out 0x12, r24 ; 18 |
| 86e: 88 b3 in r24, 0x18 ; 24 |
| 870: 81 7f andi r24, 0xF1 ; 241 |
| 872: 88 bb out 0x18, r24 ; 24 |
| 874: c1 9a sbi 0x18, 1 ; 24 |
| 876: 81 e0 ldi r24, 0x01 ; 1 |
| 878: 90 e0 ldi r25, 0x00 ; 0 |
| 87a: ac de rcall .-680 ; 0x5d4 <DelayM> |
| 87c: 82 b3 in r24, 0x12 ; 18 |
| 87e: 87 7c andi r24, 0xC7 ; 199 |
| 880: 82 bb out 0x12, r24 ; 18 |
| 882: 88 b3 in r24, 0x18 ; 24 |
| 884: 81 7f andi r24, 0xF1 ; 241 |
| 886: 88 bb out 0x18, r24 ; 24 |
| 888: 80 91 ad 02 lds r24, 0x02AD |
| 88c: 90 91 ae 02 lds r25, 0x02AE |
| 890: 8e 0d add r24, r14 |
| 892: 9f 1d adc r25, r15 |
| 894: 20 91 7b 00 lds r18, 0x007B |
| 898: 30 91 7c 00 lds r19, 0x007C |
| 89c: 82 17 cp r24, r18 |
| 89e: 93 07 cpc r25, r19 |
| 8a0: 28 f4 brcc .+10 ; 0x8ac <MotorTon+0x28e> |
| 8a2: 86 e3 ldi r24, 0x36 ; 54 |
| 8a4: a6 d5 rcall .+2892 ; 0x13f2 <uart_putchar> |
| 8a6: 56 e0 ldi r21, 0x06 ; 6 |
| 8a8: b5 2e mov r11, r21 |
| 8aa: 05 c0 rjmp .+10 ; 0x8b6 <MotorTon+0x298> |
| 8ac: 0f 5f subi r16, 0xFF ; 255 |
| 8ae: 1f 4f sbci r17, 0xFF ; 255 |
| 8b0: 08 15 cp r16, r8 |
| 8b2: 19 05 cpc r17, r9 |
| 8b4: a9 f6 brne .-86 ; 0x860 <MotorTon+0x242> |
| 8b6: 17 b8 out 0x07, r1 ; 7 |
| 8b8: 82 b3 in r24, 0x12 ; 18 |
| 8ba: 87 7c andi r24, 0xC7 ; 199 |
| 8bc: 82 bb out 0x12, r24 ; 18 |
| 8be: 88 b3 in r24, 0x18 ; 24 |
| 8c0: 81 7f andi r24, 0xF1 ; 241 |
| 8c2: 88 bb out 0x18, r24 ; 24 |
| 8c4: 94 9a sbi 0x12, 4 ; 18 |
| 8c6: 95 9a sbi 0x12, 5 ; 18 |
| 8c8: 10 92 7c 00 sts 0x007C, r1 |
| 8cc: 10 92 7b 00 sts 0x007B, r1 |
| 8d0: 00 e0 ldi r16, 0x00 ; 0 |
| 8d2: 10 e0 ldi r17, 0x00 ; 0 |
| 8d4: ff 24 eor r15, r15 |
| 8d6: c3 9a sbi 0x18, 3 ; 24 |
| 8d8: 80 e0 ldi r24, 0x00 ; 0 |
| 8da: 90 e0 ldi r25, 0x00 ; 0 |
| 8dc: fa db rcall .-2060 ; 0xd2 <MessAD> |
| 8de: c3 97 sbiw r24, 0x33 ; 51 |
| 8e0: 1c f0 brlt .+6 ; 0x8e8 <MotorTon+0x2ca> |
| 8e2: 51 e0 ldi r21, 0x01 ; 1 |
| 8e4: f5 2a or r15, r21 |
| 8e6: 02 c0 rjmp .+4 ; 0x8ec <MotorTon+0x2ce> |
| 8e8: 8e ef ldi r24, 0xFE ; 254 |
| 8ea: f8 22 and r15, r24 |
| 8ec: 18 ba out 0x18, r1 ; 24 |
| 8ee: 0f 5f subi r16, 0xFF ; 255 |
| 8f0: 1f 4f sbci r17, 0xFF ; 255 |
| 8f2: 09 37 cpi r16, 0x79 ; 121 |
| 8f4: 11 05 cpc r17, r1 |
| 8f6: 79 f7 brne .-34 ; 0x8d6 <MotorTon+0x2b8> |
| 8f8: 82 b3 in r24, 0x12 ; 18 |
| 8fa: 87 7c andi r24, 0xC7 ; 199 |
| 8fc: 82 bb out 0x12, r24 ; 18 |
| 8fe: 88 b3 in r24, 0x18 ; 24 |
| 900: 81 7f andi r24, 0xF1 ; 241 |
| 902: 88 bb out 0x18, r24 ; 24 |
| 904: 93 9a sbi 0x12, 3 ; 18 |
| 906: 95 9a sbi 0x12, 5 ; 18 |
| 908: 00 e0 ldi r16, 0x00 ; 0 |
| 90a: 10 e0 ldi r17, 0x00 ; 0 |
| 90c: c2 9a sbi 0x18, 2 ; 24 |
| 90e: 81 e0 ldi r24, 0x01 ; 1 |
| 910: 90 e0 ldi r25, 0x00 ; 0 |
| 912: df db rcall .-2114 ; 0xd2 <MessAD> |
| 914: c3 97 sbiw r24, 0x33 ; 51 |
| 916: 1c f0 brlt .+6 ; 0x91e <MotorTon+0x300> |
| 918: 42 e0 ldi r20, 0x02 ; 2 |
| 91a: f4 2a or r15, r20 |
| 91c: 02 c0 rjmp .+4 ; 0x922 <MotorTon+0x304> |
| 91e: 5d ef ldi r21, 0xFD ; 253 |
| 920: f5 22 and r15, r21 |
| 922: 18 ba out 0x18, r1 ; 24 |
| 924: 0f 5f subi r16, 0xFF ; 255 |
| 926: 1f 4f sbci r17, 0xFF ; 255 |
| 928: 05 38 cpi r16, 0x85 ; 133 |
| 92a: 11 05 cpc r17, r1 |
| 92c: 79 f7 brne .-34 ; 0x90c <MotorTon+0x2ee> |
| 92e: 82 b3 in r24, 0x12 ; 18 |
| 930: 87 7c andi r24, 0xC7 ; 199 |
| 932: 82 bb out 0x12, r24 ; 18 |
| 934: 88 b3 in r24, 0x18 ; 24 |
| 936: 81 7f andi r24, 0xF1 ; 241 |
| 938: 88 bb out 0x18, r24 ; 24 |
| 93a: 93 9a sbi 0x12, 3 ; 18 |
| 93c: 94 9a sbi 0x12, 4 ; 18 |
| 93e: 00 e0 ldi r16, 0x00 ; 0 |
| 940: 10 e0 ldi r17, 0x00 ; 0 |
| 942: c1 9a sbi 0x18, 1 ; 24 |
| 944: 82 e0 ldi r24, 0x02 ; 2 |
| 946: 90 e0 ldi r25, 0x00 ; 0 |
| 948: c4 db rcall .-2168 ; 0xd2 <MessAD> |
| 94a: c3 97 sbiw r24, 0x33 ; 51 |
| 94c: 1c f0 brlt .+6 ; 0x954 <MotorTon+0x336> |
| 94e: 84 e0 ldi r24, 0x04 ; 4 |
| 950: f8 2a or r15, r24 |
| 952: 02 c0 rjmp .+4 ; 0x958 <MotorTon+0x33a> |
| 954: 4b ef ldi r20, 0xFB ; 251 |
| 956: f4 22 and r15, r20 |
| 958: 18 ba out 0x18, r1 ; 24 |
| 95a: 0f 5f subi r16, 0xFF ; 255 |
| 95c: 1f 4f sbci r17, 0xFF ; 255 |
| 95e: 0f 36 cpi r16, 0x6F ; 111 |
| 960: 11 05 cpc r17, r1 |
| 962: 79 f7 brne .-34 ; 0x942 <MotorTon+0x324> |
| 964: 82 b3 in r24, 0x12 ; 18 |
| 966: 87 7c andi r24, 0xC7 ; 199 |
| 968: 82 bb out 0x12, r24 ; 18 |
| 96a: 88 b3 in r24, 0x18 ; 24 |
| 96c: 81 7f andi r24, 0xF1 ; 241 |
| 96e: 88 bb out 0x18, r24 ; 24 |
| 970: 81 e0 ldi r24, 0x01 ; 1 |
| 972: 87 b9 out 0x07, r24 ; 7 |
| 974: 93 9a sbi 0x12, 3 ; 18 |
| 976: 00 e0 ldi r16, 0x00 ; 0 |
| 978: 10 e0 ldi r17, 0x00 ; 0 |
| 97a: c2 9a sbi 0x18, 2 ; 24 |
| 97c: 80 e0 ldi r24, 0x00 ; 0 |
| 97e: 90 e0 ldi r25, 0x00 ; 0 |
| 980: a8 db rcall .-2224 ; 0xd2 <MessAD> |
| 982: c3 97 sbiw r24, 0x33 ; 51 |
| 984: 1c f0 brlt .+6 ; 0x98c <MotorTon+0x36e> |
| 986: 57 ef ldi r21, 0xF7 ; 247 |
| 988: f5 22 and r15, r21 |
| 98a: 02 c0 rjmp .+4 ; 0x990 <MotorTon+0x372> |
| 98c: 88 e0 ldi r24, 0x08 ; 8 |
| 98e: f8 2a or r15, r24 |
| 990: 18 ba out 0x18, r1 ; 24 |
| 992: 0f 5f subi r16, 0xFF ; 255 |
| 994: 1f 4f sbci r17, 0xFF ; 255 |
| 996: 09 37 cpi r16, 0x79 ; 121 |
| 998: 11 05 cpc r17, r1 |
| 99a: 79 f7 brne .-34 ; 0x97a <MotorTon+0x35c> |
| 99c: 95 9a sbi 0x12, 5 ; 18 |
| 99e: 00 e0 ldi r16, 0x00 ; 0 |
| 9a0: 10 e0 ldi r17, 0x00 ; 0 |
| 9a2: c2 9a sbi 0x18, 2 ; 24 |
| 9a4: 82 e0 ldi r24, 0x02 ; 2 |
| 9a6: 90 e0 ldi r25, 0x00 ; 0 |
| 9a8: 94 db rcall .-2264 ; 0xd2 <MessAD> |
| 9aa: c3 97 sbiw r24, 0x33 ; 51 |
| 9ac: 1c f0 brlt .+6 ; 0x9b4 <MotorTon+0x396> |
| 9ae: 4f ed ldi r20, 0xDF ; 223 |
| 9b0: f4 22 and r15, r20 |
| 9b2: 02 c0 rjmp .+4 ; 0x9b8 <MotorTon+0x39a> |
| 9b4: 50 e2 ldi r21, 0x20 ; 32 |
| 9b6: f5 2a or r15, r21 |
| 9b8: 18 ba out 0x18, r1 ; 24 |
| 9ba: 0f 5f subi r16, 0xFF ; 255 |
| 9bc: 1f 4f sbci r17, 0xFF ; 255 |
| 9be: 05 38 cpi r16, 0x85 ; 133 |
| 9c0: 11 05 cpc r17, r1 |
| 9c2: 79 f7 brne .-34 ; 0x9a2 <MotorTon+0x384> |
| 9c4: 82 b3 in r24, 0x12 ; 18 |
| 9c6: 87 7c andi r24, 0xC7 ; 199 |
| 9c8: 82 bb out 0x12, r24 ; 18 |
| 9ca: 88 b3 in r24, 0x18 ; 24 |
| 9cc: 81 7f andi r24, 0xF1 ; 241 |
| 9ce: 88 bb out 0x18, r24 ; 24 |
| 9d0: 82 b3 in r24, 0x12 ; 18 |
| 9d2: 87 7c andi r24, 0xC7 ; 199 |
| 9d4: 82 bb out 0x12, r24 ; 18 |
| 9d6: 88 b3 in r24, 0x18 ; 24 |
| 9d8: 81 7f andi r24, 0xF1 ; 241 |
| 9da: 88 bb out 0x18, r24 ; 24 |
| 9dc: 94 9a sbi 0x12, 4 ; 18 |
| 9de: 00 e0 ldi r16, 0x00 ; 0 |
| 9e0: 10 e0 ldi r17, 0x00 ; 0 |
| 9e2: c1 9a sbi 0x18, 1 ; 24 |
| 9e4: 81 e0 ldi r24, 0x01 ; 1 |
| 9e6: 90 e0 ldi r25, 0x00 ; 0 |
| 9e8: 74 db rcall .-2328 ; 0xd2 <MessAD> |
| 9ea: c3 97 sbiw r24, 0x33 ; 51 |
| 9ec: 1c f0 brlt .+6 ; 0x9f4 <MotorTon+0x3d6> |
| 9ee: 8f ee ldi r24, 0xEF ; 239 |
| 9f0: f8 22 and r15, r24 |
| 9f2: 02 c0 rjmp .+4 ; 0x9f8 <MotorTon+0x3da> |
| 9f4: 40 e1 ldi r20, 0x10 ; 16 |
| 9f6: f4 2a or r15, r20 |
| 9f8: 18 ba out 0x18, r1 ; 24 |
| 9fa: 0f 5f subi r16, 0xFF ; 255 |
| 9fc: 1f 4f sbci r17, 0xFF ; 255 |
| 9fe: 0f 36 cpi r16, 0x6F ; 111 |
| a00: 11 05 cpc r17, r1 |
| a02: 79 f7 brne .-34 ; 0x9e2 <MotorTon+0x3c4> |
| a04: 82 b3 in r24, 0x12 ; 18 |
| a06: 87 7c andi r24, 0xC7 ; 199 |
| a08: 82 bb out 0x12, r24 ; 18 |
| a0a: 88 b3 in r24, 0x18 ; 24 |
| a0c: 81 7f andi r24, 0xF1 ; 241 |
| a0e: 88 bb out 0x18, r24 ; 24 |
| a10: 78 94 sei |
| a12: 80 91 67 00 lds r24, 0x0067 |
| a16: fe 01 movw r30, r28 |
| a18: e8 0f add r30, r24 |
| a1a: f1 1d adc r31, r1 |
| a1c: 21 81 ldd r18, Z+1 ; 0x01 |
| a1e: 84 e0 ldi r24, 0x04 ; 4 |
| a20: 90 e0 ldi r25, 0x00 ; 0 |
| a22: 82 1b sub r24, r18 |
| a24: 91 09 sbc r25, r1 |
| a26: 2c e2 ldi r18, 0x2C ; 44 |
| a28: 31 e0 ldi r19, 0x01 ; 1 |
| a2a: ac 01 movw r20, r24 |
| a2c: 42 9f mul r20, r18 |
| a2e: c0 01 movw r24, r0 |
| a30: 43 9f mul r20, r19 |
| a32: 90 0d add r25, r0 |
| a34: 52 9f mul r21, r18 |
| a36: 90 0d add r25, r0 |
| a38: 11 24 eor r1, r1 |
| a3a: 4b d3 rcall .+1686 ; 0x10d2 <Delay_ms> |
| a3c: 8f 2d mov r24, r15 |
| a3e: 99 27 eor r25, r25 |
| a40: 80 fd sbrc r24, 0 |
| a42: 05 c0 rjmp .+10 ; 0xa4e <MotorTon+0x430> |
| a44: 81 e4 ldi r24, 0x41 ; 65 |
| a46: 8c b9 out 0x0c, r24 ; 12 |
| a48: bb 24 eor r11, r11 |
| a4a: b3 94 inc r11 |
| a4c: 25 c0 rjmp .+74 ; 0xa98 <MotorTon+0x47a> |
| a4e: 81 fd sbrc r24, 1 |
| a50: 05 c0 rjmp .+10 ; 0xa5c <MotorTon+0x43e> |
| a52: 82 e4 ldi r24, 0x42 ; 66 |
| a54: 8c b9 out 0x0c, r24 ; 12 |
| a56: 42 e0 ldi r20, 0x02 ; 2 |
| a58: b4 2e mov r11, r20 |
| a5a: 1e c0 rjmp .+60 ; 0xa98 <MotorTon+0x47a> |
| a5c: 82 fd sbrc r24, 2 |
| a5e: 05 c0 rjmp .+10 ; 0xa6a <MotorTon+0x44c> |
| a60: 83 e4 ldi r24, 0x43 ; 67 |
| a62: 8c b9 out 0x0c, r24 ; 12 |
| a64: 33 e0 ldi r19, 0x03 ; 3 |
| a66: b3 2e mov r11, r19 |
| a68: 17 c0 rjmp .+46 ; 0xa98 <MotorTon+0x47a> |
| a6a: 83 fd sbrc r24, 3 |
| a6c: 05 c0 rjmp .+10 ; 0xa78 <MotorTon+0x45a> |
| a6e: 81 e6 ldi r24, 0x61 ; 97 |
| a70: 8c b9 out 0x0c, r24 ; 12 |
| a72: 24 e0 ldi r18, 0x04 ; 4 |
| a74: b2 2e mov r11, r18 |
| a76: 10 c0 rjmp .+32 ; 0xa98 <MotorTon+0x47a> |
| a78: 84 fd sbrc r24, 4 |
| a7a: 05 c0 rjmp .+10 ; 0xa86 <MotorTon+0x468> |
| a7c: 82 e6 ldi r24, 0x62 ; 98 |
| a7e: 8c b9 out 0x0c, r24 ; 12 |
| a80: 95 e0 ldi r25, 0x05 ; 5 |
| a82: b9 2e mov r11, r25 |
| a84: 09 c0 rjmp .+18 ; 0xa98 <MotorTon+0x47a> |
| a86: 85 fd sbrc r24, 5 |
| a88: 05 c0 rjmp .+10 ; 0xa94 <MotorTon+0x476> |
| a8a: 83 e6 ldi r24, 0x63 ; 99 |
| a8c: 8c b9 out 0x0c, r24 ; 12 |
| a8e: 86 e0 ldi r24, 0x06 ; 6 |
| a90: b8 2e mov r11, r24 |
| a92: 02 c0 rjmp .+4 ; 0xa98 <MotorTon+0x47a> |
| a94: bb 20 and r11, r11 |
| a96: 19 f0 breq .+6 ; 0xa9e <MotorTon+0x480> |
| a98: 88 ee ldi r24, 0xE8 ; 232 |
| a9a: 93 e0 ldi r25, 0x03 ; 3 |
| a9c: 1a d3 rcall .+1588 ; 0x10d2 <Delay_ms> |
| a9e: 8b 2d mov r24, r11 |
| aa0: 86 dd rcall .-1268 ; 0x5ae <RotBlink> |
| aa2: 8e e2 ldi r24, 0x2E ; 46 |
| aa4: a6 d4 rcall .+2380 ; 0x13f2 <uart_putchar> |
| aa6: 25 96 adiw r28, 0x05 ; 5 |
| aa8: 0f b6 in r0, 0x3f ; 63 |
| aaa: f8 94 cli |
| aac: de bf out 0x3e, r29 ; 62 |
| aae: 0f be out 0x3f, r0 ; 63 |
| ab0: cd bf out 0x3d, r28 ; 61 |
| ab2: df 91 pop r29 |
| ab4: cf 91 pop r28 |
| ab6: 1f 91 pop r17 |
| ab8: 0f 91 pop r16 |
| aba: ff 90 pop r15 |
| abc: ef 90 pop r14 |
| abe: df 90 pop r13 |
| ac0: cf 90 pop r12 |
| ac2: bf 90 pop r11 |
| ac4: 9f 90 pop r9 |
| ac6: 8f 90 pop r8 |
| ac8: 08 95 ret |
| |
| 00000aca <Anwerfen>: |
| aca: af 92 push r10 |
| acc: bf 92 push r11 |
| ace: cf 92 push r12 |
| ad0: df 92 push r13 |
| ad2: ef 92 push r14 |
| ad4: ff 92 push r15 |
| ad6: 0f 93 push r16 |
| ad8: 1f 93 push r17 |
| ada: cf 93 push r28 |
| adc: df 93 push r29 |
| ade: 18 2f mov r17, r24 |
| ae0: 10 92 78 00 sts 0x0078, r1 |
| ae4: 43 98 cbi 0x08, 3 ; 8 |
| ae6: 85 e0 ldi r24, 0x05 ; 5 |
| ae8: 90 e0 ldi r25, 0x00 ; 0 |
| aea: 90 93 7a 00 sts 0x007A, r25 |
| aee: 80 93 79 00 sts 0x0079, r24 |
| af2: 84 dc rcall .-1784 ; 0x3fc <SetPWM> |
| af4: 25 db rcall .-2486 ; 0x140 <Manuell> |
| af6: 88 ec ldi r24, 0xC8 ; 200 |
| af8: 90 e0 ldi r25, 0x00 ; 0 |
| afa: eb d2 rcall .+1494 ; 0x10d2 <Delay_ms> |
| afc: c1 2f mov r28, r17 |
| afe: dd 27 eor r29, r29 |
| b00: d0 93 7a 00 sts 0x007A, r29 |
| b04: c0 93 79 00 sts 0x0079, r28 |
| b08: 1c e2 ldi r17, 0x2C ; 44 |
| b0a: a1 2e mov r10, r17 |
| b0c: 11 e0 ldi r17, 0x01 ; 1 |
| b0e: b1 2e mov r11, r17 |
| b10: c1 2c mov r12, r1 |
| b12: d1 2c mov r13, r1 |
| b14: ee 24 eor r14, r14 |
| b16: ff 24 eor r15, r15 |
| b18: 87 01 movw r16, r14 |
| b1a: 0e c0 rjmp .+28 ; 0xb38 <Anwerfen+0x6e> |
| b1c: 80 91 6e 00 lds r24, 0x006E |
| b20: 88 23 and r24, r24 |
| b22: 11 f4 brne .+4 ; 0xb28 <Anwerfen+0x5e> |
| b24: 51 d3 rcall .+1698 ; 0x11c8 <SendUart> |
| b26: 01 c0 rjmp .+2 ; 0xb2a <Anwerfen+0x60> |
| b28: 52 d5 rcall .+2724 ; 0x15ce <DatenUebertragung> |
| b2a: 84 e6 ldi r24, 0x64 ; 100 |
| b2c: 95 dc rcall .-1750 ; 0x458 <Wait> |
| b2e: 08 94 sec |
| b30: e1 1c adc r14, r1 |
| b32: f1 1c adc r15, r1 |
| b34: 01 1d adc r16, r1 |
| b36: 11 1d adc r17, r1 |
| b38: ea 14 cp r14, r10 |
| b3a: fb 04 cpc r15, r11 |
| b3c: 0c 05 cpc r16, r12 |
| b3e: 1d 05 cpc r17, r13 |
| b40: 69 f7 brne .-38 ; 0xb1c <Anwerfen+0x52> |
| b42: c6 01 movw r24, r12 |
| b44: b5 01 movw r22, r10 |
| b46: 2f e0 ldi r18, 0x0F ; 15 |
| b48: 30 e0 ldi r19, 0x00 ; 0 |
| b4a: 40 e0 ldi r20, 0x00 ; 0 |
| b4c: 50 e0 ldi r21, 0x00 ; 0 |
| b4e: 12 d7 rcall .+3620 ; 0x1974 <__udivmodsi4> |
| b50: a2 1a sub r10, r18 |
| b52: b3 0a sbc r11, r19 |
| b54: c4 0a sbc r12, r20 |
| b56: d5 0a sbc r13, r21 |
| b58: 08 94 sec |
| b5a: a1 08 sbc r10, r1 |
| b5c: b1 08 sbc r11, r1 |
| b5e: c1 08 sbc r12, r1 |
| b60: d1 08 sbc r13, r1 |
| b62: 89 e1 ldi r24, 0x19 ; 25 |
| b64: a8 16 cp r10, r24 |
| b66: b1 04 cpc r11, r1 |
| b68: c1 04 cpc r12, r1 |
| b6a: d1 04 cpc r13, r1 |
| b6c: c0 f0 brcs .+48 ; 0xb9e <Anwerfen+0xd4> |
| b6e: e8 da rcall .-2608 ; 0x140 <Manuell> |
| b70: 80 91 76 00 lds r24, 0x0076 |
| b74: 8f 5f subi r24, 0xFF ; 255 |
| b76: 80 93 76 00 sts 0x0076, r24 |
| b7a: 80 91 76 00 lds r24, 0x0076 |
| b7e: 66 e0 ldi r22, 0x06 ; 6 |
| b80: d9 d6 rcall .+3506 ; 0x1934 <__udivmodqi4> |
| b82: 90 93 76 00 sts 0x0076, r25 |
| b86: 70 da rcall .-2848 ; 0x68 <AdConvert> |
| b88: d0 93 7a 00 sts 0x007A, r29 |
| b8c: c0 93 79 00 sts 0x0079, r28 |
| b90: 35 dc rcall .-1942 ; 0x3fc <SetPWM> |
| b92: 44 9b sbis 0x08, 4 ; 8 |
| b94: bf cf rjmp .-130 ; 0xb14 <Anwerfen+0x4a> |
| b96: 82 b3 in r24, 0x12 ; 18 |
| b98: 80 58 subi r24, 0x80 ; 128 |
| b9a: 82 bb out 0x12, r24 ; 18 |
| b9c: bb cf rjmp .-138 ; 0xb14 <Anwerfen+0x4a> |
| b9e: df 91 pop r29 |
| ba0: cf 91 pop r28 |
| ba2: 1f 91 pop r17 |
| ba4: 0f 91 pop r16 |
| ba6: ff 90 pop r15 |
| ba8: ef 90 pop r14 |
| baa: df 90 pop r13 |
| bac: cf 90 pop r12 |
| bae: bf 90 pop r11 |
| bb0: af 90 pop r10 |
| bb2: 08 95 ret |
| |
| 00000bb4 <main>: |
| bb4: cf e5 ldi r28, 0x5F ; 95 |
| bb6: d4 e0 ldi r29, 0x04 ; 4 |
| bb8: de bf out 0x3e, r29 ; 62 |
| bba: cd bf out 0x3d, r28 ; 61 |
| bbc: 88 e0 ldi r24, 0x08 ; 8 |
| bbe: 84 bb out 0x14, r24 ; 20 |
| bc0: 85 bb out 0x15, r24 ; 21 |
| bc2: 8a eb ldi r24, 0xBA ; 186 |
| bc4: 81 bb out 0x11, r24 ; 17 |
| bc6: 12 ba out 0x12, r1 ; 18 |
| bc8: 8e e0 ldi r24, 0x0E ; 14 |
| bca: 87 bb out 0x17, r24 ; 23 |
| bcc: 81 e3 ldi r24, 0x31 ; 49 |
| bce: 88 bb out 0x18, r24 ; 24 |
| bd0: 88 b3 in r24, 0x18 ; 24 |
| bd2: 80 6c ori r24, 0xC0 ; 192 |
| bd4: 88 bb out 0x18, r24 ; 24 |
| bd6: b6 9b sbis 0x16, 6 ; 22 |
| bd8: 06 c0 rjmp .+12 ; 0xbe6 <main+0x32> |
| bda: b7 9b sbis 0x16, 7 ; 22 |
| bdc: 02 c0 rjmp .+4 ; 0xbe2 <main+0x2e> |
| bde: 81 e0 ldi r24, 0x01 ; 1 |
| be0: 07 c0 rjmp .+14 ; 0xbf0 <main+0x3c> |
| be2: 82 e0 ldi r24, 0x02 ; 2 |
| be4: 05 c0 rjmp .+10 ; 0xbf0 <main+0x3c> |
| be6: b7 9b sbis 0x16, 7 ; 22 |
| be8: 02 c0 rjmp .+4 ; 0xbee <main+0x3a> |
| bea: 83 e0 ldi r24, 0x03 ; 3 |
| bec: 01 c0 rjmp .+2 ; 0xbf0 <main+0x3c> |
| bee: 84 e0 ldi r24, 0x04 ; 4 |
| bf0: 80 93 67 00 sts 0x0067, r24 |
| bf4: 06 d5 rcall .+2572 ; 0x1602 <UART_Init> |
| bf6: 50 d2 rcall .+1184 ; 0x1098 <Timer0_Init> |
| bf8: 78 94 sei |
| bfa: 23 dc rcall .-1978 ; 0x442 <PWM_Init> |
| bfc: 80 e5 ldi r24, 0x50 ; 80 |
| bfe: 81 d2 rcall .+1282 ; 0x1102 <InitIC2_Slave> |
| c00: 3d d1 rcall .+634 ; 0xe7c <InitPPM> |
| c02: 85 e6 ldi r24, 0x65 ; 101 |
| c04: 90 e0 ldi r25, 0x00 ; 0 |
| c06: 51 d2 rcall .+1186 ; 0x10aa <SetDelay> |
| c08: 86 e6 ldi r24, 0x66 ; 102 |
| c0a: 90 e0 ldi r25, 0x00 ; 0 |
| c0c: 4e d2 rcall .+1180 ; 0x10aa <SetDelay> |
| c0e: 87 e6 ldi r24, 0x67 ; 103 |
| c10: 90 e0 ldi r25, 0x00 ; 0 |
| c12: 4b d2 rcall .+1174 ; 0x10aa <SetDelay> |
| c14: ec 01 movw r28, r24 |
| c16: 8e ef ldi r24, 0xFE ; 254 |
| c18: 90 e0 ldi r25, 0x00 ; 0 |
| c1a: 47 d2 rcall .+1166 ; 0x10aa <SetDelay> |
| c1c: 6c 01 movw r12, r24 |
| c1e: 8d ee ldi r24, 0xED ; 237 |
| c20: 93 e0 ldi r25, 0x03 ; 3 |
| c22: 43 d2 rcall .+1158 ; 0x10aa <SetDelay> |
| c24: 8c 01 movw r16, r24 |
| c26: 8e ee ldi r24, 0xEE ; 238 |
| c28: 93 e0 ldi r25, 0x03 ; 3 |
| c2a: 3f d2 rcall .+1150 ; 0x10aa <SetDelay> |
| c2c: 03 c0 rjmp .+6 ; 0xc34 <main+0x80> |
| c2e: 20 dc rcall .-1984 ; 0x470 <SollwertErmittlung> |
| c30: 88 23 and r24, r24 |
| c32: 21 f4 brne .+8 ; 0xc3c <main+0x88> |
| c34: ce 01 movw r24, r28 |
| c36: 42 d2 rcall .+1156 ; 0x10bc <CheckDelay> |
| c38: 88 23 and r24, r24 |
| c3a: c9 f3 breq .-14 ; 0xc2e <main+0x7a> |
| c3c: 97 9a sbi 0x12, 7 ; 18 |
| c3e: 10 92 7a 00 sts 0x007A, r1 |
| c42: 10 92 79 00 sts 0x0079, r1 |
| c46: da db rcall .-2124 ; 0x3fc <SetPWM> |
| c48: 88 e0 ldi r24, 0x08 ; 8 |
| c4a: 80 bf out 0x30, r24 ; 48 |
| c4c: 81 e0 ldi r24, 0x01 ; 1 |
| c4e: 87 b9 out 0x07, r24 ; 7 |
| c50: 8a e0 ldi r24, 0x0A ; 10 |
| c52: 90 e0 ldi r25, 0x00 ; 0 |
| c54: 2a d2 rcall .+1108 ; 0x10aa <SetDelay> |
| c56: ec 01 movw r28, r24 |
| c58: 81 e0 ldi r24, 0x01 ; 1 |
| c5a: 90 e0 ldi r25, 0x00 ; 0 |
| c5c: 90 93 91 03 sts 0x0391, r25 |
| c60: 80 93 90 03 sts 0x0390, r24 |
| c64: 10 92 91 00 sts 0x0091, r1 |
| c68: 10 92 90 00 sts 0x0090, r1 |
| c6c: 01 dc rcall .-2046 ; 0x470 <SollwertErmittlung> |
| c6e: 88 23 and r24, r24 |
| c70: 09 f4 brne .+2 ; 0xc74 <main+0xc0> |
| c72: d5 dc rcall .-1622 ; 0x61e <MotorTon> |
| c74: 81 e3 ldi r24, 0x31 ; 49 |
| c76: 88 bb out 0x18, r24 ; 24 |
| c78: ee 24 eor r14, r14 |
| c7a: fa db rcall .-2060 ; 0x470 <SollwertErmittlung> |
| c7c: 99 27 eor r25, r25 |
| c7e: 90 93 7a 00 sts 0x007A, r25 |
| c82: 80 93 79 00 sts 0x0079, r24 |
| c86: 80 91 76 00 lds r24, 0x0076 |
| c8a: 8e 15 cp r24, r14 |
| c8c: 51 f0 breq .+20 ; 0xca2 <main+0xee> |
| c8e: 10 92 64 00 sts 0x0064, r1 |
| c92: 10 92 63 00 sts 0x0063, r1 |
| c96: 8a ef ldi r24, 0xFA ; 250 |
| c98: 90 e0 ldi r25, 0x00 ; 0 |
| c9a: 07 d2 rcall .+1038 ; 0x10aa <SetDelay> |
| c9c: ec 01 movw r28, r24 |
| c9e: e0 90 76 00 lds r14, 0x0076 |
| ca2: 80 91 79 00 lds r24, 0x0079 |
| ca6: 90 91 7a 00 lds r25, 0x007A |
| caa: 89 2b or r24, r25 |
| cac: d1 f4 brne .+52 ; 0xce2 <main+0x12e> |
| cae: 10 92 89 00 sts 0x0089, r1 |
| cb2: 10 92 63 00 sts 0x0063, r1 |
| cb6: c5 01 movw r24, r10 |
| cb8: 01 d2 rcall .+1026 ; 0x10bc <CheckDelay> |
| cba: 88 23 and r24, r24 |
| cbc: e9 f0 breq .+58 ; 0xcf8 <main+0x144> |
| cbe: 10 92 78 00 sts 0x0078, r1 |
| cc2: 43 98 cbi 0x08, 3 ; 8 |
| cc4: 91 e0 ldi r25, 0x01 ; 1 |
| cc6: 90 93 64 00 sts 0x0064, r25 |
| cca: 82 b3 in r24, 0x12 ; 18 |
| ccc: 87 7c andi r24, 0xC7 ; 199 |
| cce: 82 bb out 0x12, r24 ; 18 |
| cd0: 9f bd out 0x2f, r25 ; 47 |
| cd2: 81 e4 ldi r24, 0x41 ; 65 |
| cd4: 85 bd out 0x25, r24 ; 37 |
| cd6: 8e e0 ldi r24, 0x0E ; 14 |
| cd8: 87 bb out 0x17, r24 ; 23 |
| cda: 88 b3 in r24, 0x18 ; 24 |
| cdc: 81 7f andi r24, 0xF1 ; 241 |
| cde: 88 bb out 0x18, r24 ; 24 |
| ce0: 0b c0 rjmp .+22 ; 0xcf8 <main+0x144> |
| ce2: 80 91 64 00 lds r24, 0x0064 |
| ce6: 88 23 and r24, r24 |
| ce8: 19 f0 breq .+6 ; 0xcf0 <main+0x13c> |
| cea: 81 e0 ldi r24, 0x01 ; 1 |
| cec: 80 93 89 00 sts 0x0089, r24 |
| cf0: 8c ed ldi r24, 0xDC ; 220 |
| cf2: 95 e0 ldi r25, 0x05 ; 5 |
| cf4: da d1 rcall .+948 ; 0x10aa <SetDelay> |
| cf6: 5c 01 movw r10, r24 |
| cf8: 80 91 64 00 lds r24, 0x0064 |
| cfc: 88 23 and r24, r24 |
| cfe: 21 f0 breq .+8 ; 0xd08 <main+0x154> |
| d00: 10 92 7a 00 sts 0x007A, r1 |
| d04: 10 92 79 00 sts 0x0079, r1 |
| d08: 79 db rcall .-2318 ; 0x3fc <SetPWM> |
| d0a: 80 91 63 00 lds r24, 0x0063 |
| d0e: 8f 5f subi r24, 0xFF ; 255 |
| d10: 80 93 63 00 sts 0x0063, r24 |
| d14: 81 30 cpi r24, 0x01 ; 1 |
| d16: 09 f0 breq .+2 ; 0xd1a <main+0x166> |
| d18: b0 cf rjmp .-160 ; 0xc7a <main+0xc6> |
| d1a: 80 91 64 00 lds r24, 0x0064 |
| d1e: 81 11 cpse r24, r1 |
| d20: 97 9a sbi 0x12, 7 ; 18 |
| d22: c6 01 movw r24, r12 |
| d24: cb d1 rcall .+918 ; 0x10bc <CheckDelay> |
| d26: 88 23 and r24, r24 |
| d28: a9 f1 breq .+106 ; 0xd94 <main+0x1e0> |
| d2a: 82 e3 ldi r24, 0x32 ; 50 |
| d2c: 90 e0 ldi r25, 0x00 ; 0 |
| d2e: bd d1 rcall .+890 ; 0x10aa <SetDelay> |
| d30: 6c 01 movw r12, r24 |
| d32: 80 91 7e 00 lds r24, 0x007E |
| d36: 48 2f mov r20, r24 |
| d38: 55 27 eor r21, r21 |
| d3a: 20 91 7b 00 lds r18, 0x007B |
| d3e: 30 91 7c 00 lds r19, 0x007C |
| d42: 42 17 cp r20, r18 |
| d44: 53 07 cpc r21, r19 |
| d46: 10 f4 brcc .+4 ; 0xd4c <main+0x198> |
| d48: 8f 5f subi r24, 0xFF ; 255 |
| d4a: 04 c0 rjmp .+8 ; 0xd54 <main+0x1a0> |
| d4c: 24 17 cp r18, r20 |
| d4e: 35 07 cpc r19, r21 |
| d50: 18 f4 brcc .+6 ; 0xd58 <main+0x1a4> |
| d52: 81 50 subi r24, 0x01 ; 1 |
| d54: 80 93 7e 00 sts 0x007E, r24 |
| d58: 29 3c cpi r18, 0xC9 ; 201 |
| d5a: 31 05 cpc r19, r1 |
| d5c: 48 f0 brcs .+18 ; 0xd70 <main+0x1bc> |
| d5e: 80 91 65 00 lds r24, 0x0065 |
| d62: 98 2f mov r25, r24 |
| d64: 92 95 swap r25 |
| d66: 96 95 lsr r25 |
| d68: 97 70 andi r25, 0x07 ; 7 |
| d6a: 89 1b sub r24, r25 |
| d6c: 80 93 65 00 sts 0x0065, r24 |
| d70: 80 91 7e 00 lds r24, 0x007E |
| d74: 90 91 65 00 lds r25, 0x0065 |
| d78: 89 37 cpi r24, 0x79 ; 121 |
| d7a: 38 f0 brcs .+14 ; 0xd8a <main+0x1d6> |
| d7c: 99 23 and r25, r25 |
| d7e: 19 f0 breq .+6 ; 0xd86 <main+0x1d2> |
| d80: 91 50 subi r25, 0x01 ; 1 |
| d82: 90 93 65 00 sts 0x0065, r25 |
| d86: ab 9a sbi 0x15, 3 ; 21 |
| d88: 05 c0 rjmp .+10 ; 0xd94 <main+0x1e0> |
| d8a: 9f 3f cpi r25, 0xFF ; 255 |
| d8c: 19 f0 breq .+6 ; 0xd94 <main+0x1e0> |
| d8e: 9f 5f subi r25, 0xFF ; 255 |
| d90: 90 93 65 00 sts 0x0065, r25 |
| d94: c8 01 movw r24, r16 |
| d96: 92 d1 rcall .+804 ; 0x10bc <CheckDelay> |
| d98: 88 23 and r24, r24 |
| d9a: b9 f0 breq .+46 ; 0xdca <main+0x216> |
| d9c: 8a e0 ldi r24, 0x0A ; 10 |
| d9e: 90 e0 ldi r25, 0x00 ; 0 |
| da0: 84 d1 rcall .+776 ; 0x10aa <SetDelay> |
| da2: 8c 01 movw r16, r24 |
| da4: 80 91 8a 00 lds r24, 0x008A |
| da8: 90 91 8b 00 lds r25, 0x008B |
| dac: 90 93 8d 00 sts 0x008D, r25 |
| db0: 80 93 8c 00 sts 0x008C, r24 |
| db4: 10 92 8b 00 sts 0x008B, r1 |
| db8: 10 92 8a 00 sts 0x008A, r1 |
| dbc: 80 91 93 00 lds r24, 0x0093 |
| dc0: 88 23 and r24, r24 |
| dc2: 19 f4 brne .+6 ; 0xdca <main+0x216> |
| dc4: 81 e0 ldi r24, 0x01 ; 1 |
| dc6: 80 93 66 00 sts 0x0066, r24 |
| dca: ce 01 movw r24, r28 |
| dcc: 77 d1 rcall .+750 ; 0x10bc <CheckDelay> |
| dce: 88 23 and r24, r24 |
| dd0: 31 f0 breq .+12 ; 0xdde <main+0x22a> |
| dd2: 80 91 8c 00 lds r24, 0x008C |
| dd6: 90 91 8d 00 lds r25, 0x008D |
| dda: 89 2b or r24, r25 |
| ddc: 29 f0 breq .+10 ; 0xde8 <main+0x234> |
| dde: 80 91 89 00 lds r24, 0x0089 |
| de2: 88 23 and r24, r24 |
| de4: 09 f4 brne .+2 ; 0xde8 <main+0x234> |
| de6: 49 cf rjmp .-366 ; 0xc7a <main+0xc6> |
| de8: ff 24 eor r15, r15 |
| dea: f3 94 inc r15 |
| dec: f0 92 64 00 sts 0x0064, r15 |
| df0: 10 92 78 00 sts 0x0078, r1 |
| df4: 43 98 cbi 0x08, 3 ; 8 |
| df6: 84 e6 ldi r24, 0x64 ; 100 |
| df8: 90 e0 ldi r25, 0x00 ; 0 |
| dfa: 57 d1 rcall .+686 ; 0x10aa <SetDelay> |
| dfc: ec 01 movw r28, r24 |
| dfe: 80 91 89 00 lds r24, 0x0089 |
| e02: 88 23 and r24, r24 |
| e04: 09 f4 brne .+2 ; 0xe08 <main+0x254> |
| e06: 39 cf rjmp .-398 ; 0xc7a <main+0xc6> |
| e08: ab 98 cbi 0x15, 3 ; 21 |
| e0a: 10 92 89 00 sts 0x0089, r1 |
| e0e: 8a e0 ldi r24, 0x0A ; 10 |
| e10: 5c de rcall .-840 ; 0xaca <Anwerfen> |
| e12: 97 9a sbi 0x12, 7 ; 18 |
| e14: 10 92 64 00 sts 0x0064, r1 |
| e18: 80 91 76 00 lds r24, 0x0076 |
| e1c: 81 50 subi r24, 0x01 ; 1 |
| e1e: 80 93 76 00 sts 0x0076, r24 |
| e22: 81 e0 ldi r24, 0x01 ; 1 |
| e24: 90 e0 ldi r25, 0x00 ; 0 |
| e26: 90 93 7a 00 sts 0x007A, r25 |
| e2a: 80 93 79 00 sts 0x0079, r24 |
| e2e: e6 da rcall .-2612 ; 0x3fc <SetPWM> |
| e30: 88 b1 in r24, 0x08 ; 8 |
| e32: 8c 7f andi r24, 0xFC ; 252 |
| e34: 88 b9 out 0x08, r24 ; 8 |
| e36: f0 92 78 00 sts 0x0078, r15 |
| e3a: 88 b1 in r24, 0x08 ; 8 |
| e3c: 8a 60 ori r24, 0x0A ; 10 |
| e3e: 88 b9 out 0x08, r24 ; 8 |
| e40: 84 e1 ldi r24, 0x14 ; 20 |
| e42: 90 e0 ldi r25, 0x00 ; 0 |
| e44: 32 d1 rcall .+612 ; 0x10aa <SetDelay> |
| e46: ec 01 movw r28, r24 |
| e48: ce 01 movw r24, r28 |
| e4a: 38 d1 rcall .+624 ; 0x10bc <CheckDelay> |
| e4c: 88 23 and r24, r24 |
| e4e: e1 f3 breq .-8 ; 0xe48 <main+0x294> |
| e50: 8f e0 ldi r24, 0x0F ; 15 |
| e52: 90 e0 ldi r25, 0x00 ; 0 |
| e54: 90 93 7a 00 sts 0x007A, r25 |
| e58: 80 93 79 00 sts 0x0079, r24 |
| e5c: cf da rcall .-2658 ; 0x3fc <SetPWM> |
| e5e: 8c e2 ldi r24, 0x2C ; 44 |
| e60: 91 e0 ldi r25, 0x01 ; 1 |
| e62: 23 d1 rcall .+582 ; 0x10aa <SetDelay> |
| e64: ec 01 movw r28, r24 |
| e66: ce 01 movw r24, r28 |
| e68: 29 d1 rcall .+594 ; 0x10bc <CheckDelay> |
| e6a: 88 23 and r24, r24 |
| e6c: e1 f3 breq .-8 ; 0xe66 <main+0x2b2> |
| e6e: 82 e3 ldi r24, 0x32 ; 50 |
| e70: 90 e0 ldi r25, 0x00 ; 0 |
| e72: 1b d1 rcall .+566 ; 0x10aa <SetDelay> |
| e74: 8c 01 movw r16, r24 |
| e76: 87 e0 ldi r24, 0x07 ; 7 |
| e78: e8 2e mov r14, r24 |
| e7a: ff ce rjmp .-514 ; 0xc7a <main+0xc6> |
| |
| 00000e7c <InitPPM>: |
| // |
| void InitPPM(void) |
| //############################################################################ |
| { |
| TCCR1B |= (1<<ICES1)|(1<<ICNC1); |
| e7c: 8e b5 in r24, 0x2e ; 46 |
| e7e: 80 6c ori r24, 0xC0 ; 192 |
| e80: 8e bd out 0x2e, r24 ; 46 |
| ICP_POS_FLANKE; |
| e82: 8e b5 in r24, 0x2e ; 46 |
| e84: 80 64 ori r24, 0x40 ; 64 |
| e86: 8e bd out 0x2e, r24 ; 46 |
| ICP_INT_ENABLE; |
| e88: 89 b7 in r24, 0x39 ; 57 |
| e8a: 80 62 ori r24, 0x20 ; 32 |
| e8c: 89 bf out 0x39, r24 ; 57 |
| TIMER1_INT_ENABLE; |
| e8e: 89 b7 in r24, 0x39 ; 57 |
| e90: 84 60 ori r24, 0x04 ; 4 |
| e92: 89 bf out 0x39, r24 ; 57 |
| e94: 08 95 ret |
| |
| 00000e96 <__vector_8>: |
| } |
| |
| //############################################################################ |
| // |
| SIGNAL(SIG_OVERFLOW1) |
| //############################################################################ |
| { |
| e96: 1f 92 push r1 |
| e98: 0f 92 push r0 |
| e9a: 0f b6 in r0, 0x3f ; 63 |
| e9c: 0f 92 push r0 |
| e9e: 11 24 eor r1, r1 |
| ea0: 8f 93 push r24 |
| Timer1Overflow++; |
| ea2: 80 91 92 00 lds r24, 0x0092 |
| ea6: 8f 5f subi r24, 0xFF ; 255 |
| ea8: 80 93 92 00 sts 0x0092, r24 |
| eac: 8f 91 pop r24 |
| eae: 0f 90 pop r0 |
| eb0: 0f be out 0x3f, r0 ; 63 |
| eb2: 0f 90 pop r0 |
| eb4: 1f 90 pop r1 |
| eb6: 18 95 reti |
| |
| 00000eb8 <__vector_5>: |
| } |
| |
| //############################################################################ |
| // |
| SIGNAL(SIG_INPUT_CAPTURE1) |
| //############################################################################ |
| { |
| eb8: 1f 92 push r1 |
| eba: 0f 92 push r0 |
| ebc: 0f b6 in r0, 0x3f ; 63 |
| ebe: 0f 92 push r0 |
| ec0: 11 24 eor r1, r1 |
| ec2: 2f 93 push r18 |
| ec4: 3f 93 push r19 |
| ec6: 4f 93 push r20 |
| ec8: 5f 93 push r21 |
| eca: 8f 93 push r24 |
| ecc: 9f 93 push r25 |
| static unsigned int tim_alt; |
| static unsigned int ppm; |
| if(TCCR1B & (1<<ICES1)) // Positive Flanke |
| ece: 0e b4 in r0, 0x2e ; 46 |
| ed0: 06 fe sbrs r0, 6 |
| ed2: 0f c0 rjmp .+30 ; 0xef2 <__vector_5+0x3a> |
| { |
| Timer1Overflow = 0; |
| ed4: 10 92 92 00 sts 0x0092, r1 |
| tim_alt = ICR1; |
| ed8: 86 b5 in r24, 0x26 ; 38 |
| eda: 97 b5 in r25, 0x27 ; 39 |
| edc: 90 93 98 00 sts 0x0098, r25 |
| ee0: 80 93 97 00 sts 0x0097, r24 |
| ICP_NEG_FLANKE; |
| ee4: 8e b5 in r24, 0x2e ; 46 |
| ee6: 8f 7b andi r24, 0xBF ; 191 |
| ee8: 8e bd out 0x2e, r24 ; 46 |
| PPM_Timeout = 100; |
| eea: 84 e6 ldi r24, 0x64 ; 100 |
| eec: 80 93 93 00 sts 0x0093, r24 |
| ef0: 71 c0 rjmp .+226 ; 0xfd4 <__vector_5+0x11c> |
| } |
| else // Negative Flanke |
| { |
| ICP_POS_FLANKE; |
| ef2: 8e b5 in r24, 0x2e ; 46 |
| ef4: 80 64 ori r24, 0x40 ; 64 |
| ef6: 8e bd out 0x2e, r24 ; 46 |
| #ifdef _32KHZ |
| ppm = (ICR1 - tim_alt + (int) Timer1Overflow * 256) / 32; |
| #endif |
| #ifdef _16KHZ |
| ppm = (ICR1 - tim_alt + (int) Timer1Overflow * 512) / 32; |
| ef8: 86 b5 in r24, 0x26 ; 38 |
| efa: 97 b5 in r25, 0x27 ; 39 |
| efc: 20 91 92 00 lds r18, 0x0092 |
| f00: 40 91 97 00 lds r20, 0x0097 |
| f04: 50 91 98 00 lds r21, 0x0098 |
| f08: 84 1b sub r24, r20 |
| f0a: 95 0b sbc r25, r21 |
| f0c: 33 27 eor r19, r19 |
| f0e: 32 2f mov r19, r18 |
| f10: 22 27 eor r18, r18 |
| f12: 33 0f add r19, r19 |
| f14: 82 0f add r24, r18 |
| f16: 93 1f adc r25, r19 |
| f18: 68 94 set |
| f1a: 14 f8 bld r1, 4 |
| f1c: 96 95 lsr r25 |
| f1e: 87 95 ror r24 |
| f20: 16 94 lsr r1 |
| f22: e1 f7 brne .-8 ; 0xf1c <__vector_5+0x64> |
| f24: 90 93 96 00 sts 0x0096, r25 |
| f28: 80 93 95 00 sts 0x0095, r24 |
| #endif |
| if(ppm < 280) ppm = 280; |
| f2c: 88 51 subi r24, 0x18 ; 24 |
| f2e: 91 40 sbci r25, 0x01 ; 1 |
| f30: 30 f4 brcc .+12 ; 0xf3e <__vector_5+0x86> |
| f32: 88 e1 ldi r24, 0x18 ; 24 |
| f34: 91 e0 ldi r25, 0x01 ; 1 |
| f36: 90 93 96 00 sts 0x0096, r25 |
| f3a: 80 93 95 00 sts 0x0095, r24 |
| ppm -= 280; |
| f3e: 40 91 95 00 lds r20, 0x0095 |
| f42: 50 91 96 00 lds r21, 0x0096 |
| f46: 48 51 subi r20, 0x18 ; 24 |
| f48: 51 40 sbci r21, 0x01 ; 1 |
| if(PPM_Signal < ppm) PPM_Signal++; |
| f4a: 80 91 90 00 lds r24, 0x0090 |
| f4e: 90 91 91 00 lds r25, 0x0091 |
| f52: 84 17 cp r24, r20 |
| f54: 95 07 cpc r25, r21 |
| f56: 30 f4 brcc .+12 ; 0xf64 <__vector_5+0xac> |
| f58: 80 91 90 00 lds r24, 0x0090 |
| f5c: 90 91 91 00 lds r25, 0x0091 |
| f60: 01 96 adiw r24, 0x01 ; 1 |
| f62: 0c c0 rjmp .+24 ; 0xf7c <__vector_5+0xc4> |
| else if(PPM_Signal > ppm) PPM_Signal--; |
| f64: 80 91 90 00 lds r24, 0x0090 |
| f68: 90 91 91 00 lds r25, 0x0091 |
| f6c: 48 17 cp r20, r24 |
| f6e: 59 07 cpc r21, r25 |
| f70: 48 f4 brcc .+18 ; 0xf84 <__vector_5+0xcc> |
| f72: 80 91 90 00 lds r24, 0x0090 |
| f76: 90 91 91 00 lds r25, 0x0091 |
| f7a: 01 97 sbiw r24, 0x01 ; 1 |
| f7c: 90 93 91 00 sts 0x0091, r25 |
| f80: 80 93 90 00 sts 0x0090, r24 |
| if(FILTER_PPM) ppm = (PPM_Signal * FILTER_PPM + ppm) / (FILTER_PPM + 1); // Filtern |
| f84: 80 91 90 00 lds r24, 0x0090 |
| f88: 90 91 91 00 lds r25, 0x0091 |
| f8c: 9c 01 movw r18, r24 |
| f8e: 22 0f add r18, r18 |
| f90: 33 1f adc r19, r19 |
| f92: 22 0f add r18, r18 |
| f94: 33 1f adc r19, r19 |
| f96: 22 0f add r18, r18 |
| f98: 33 1f adc r19, r19 |
| f9a: 28 1b sub r18, r24 |
| f9c: 39 0b sbc r19, r25 |
| f9e: 24 0f add r18, r20 |
| fa0: 35 1f adc r19, r21 |
| fa2: 83 e0 ldi r24, 0x03 ; 3 |
| fa4: 36 95 lsr r19 |
| fa6: 27 95 ror r18 |
| fa8: 8a 95 dec r24 |
| faa: e1 f7 brne .-8 ; 0xfa4 <__vector_5+0xec> |
| fac: 30 93 96 00 sts 0x0096, r19 |
| fb0: 20 93 95 00 sts 0x0095, r18 |
| PPM_Signal = ppm; |
| fb4: 30 93 91 00 sts 0x0091, r19 |
| fb8: 20 93 90 00 sts 0x0090, r18 |
| if(anz_ppm_werte < 255) anz_ppm_werte++; |
| fbc: 80 91 94 00 lds r24, 0x0094 |
| fc0: 8f 3f cpi r24, 0xFF ; 255 |
| fc2: 29 f0 breq .+10 ; 0xfce <__vector_5+0x116> |
| fc4: 80 91 94 00 lds r24, 0x0094 |
| fc8: 8f 5f subi r24, 0xFF ; 255 |
| fca: 80 93 94 00 sts 0x0094, r24 |
| ZeitZumAdWandeln = 1; |
| fce: 81 e0 ldi r24, 0x01 ; 1 |
| fd0: 80 93 66 00 sts 0x0066, r24 |
| fd4: 9f 91 pop r25 |
| fd6: 8f 91 pop r24 |
| fd8: 5f 91 pop r21 |
| fda: 4f 91 pop r20 |
| fdc: 3f 91 pop r19 |
| fde: 2f 91 pop r18 |
| fe0: 0f 90 pop r0 |
| fe2: 0f be out 0x3f, r0 ; 63 |
| fe4: 0f 90 pop r0 |
| fe6: 1f 90 pop r1 |
| fe8: 18 95 reti |
| |
| 00000fea <__vector_1>: |
| } |
| } |
| |
| //############################################################################ |
| // |
| SIGNAL(SIG_INTERRUPT0) |
| //############################################################################ |
| { |
| fea: 1f 92 push r1 |
| fec: 0f 92 push r0 |
| fee: 0f b6 in r0, 0x3f ; 63 |
| ff0: 0f 92 push r0 |
| ff2: 11 24 eor r1, r1 |
| ff4: 8f 93 push r24 |
| CLR_INT0_FLAG; // IntFlag Loeschen |
| ff6: 8a b7 in r24, 0x3a ; 58 |
| ff8: 8f 7b andi r24, 0xBF ; 191 |
| ffa: 8a bf out 0x3a, r24 ; 58 |
| ffc: 8f 91 pop r24 |
| ffe: 0f 90 pop r0 |
| 1000: 0f be out 0x3f, r0 ; 63 |
| 1002: 0f 90 pop r0 |
| 1004: 1f 90 pop r1 |
| 1006: 18 95 reti |
| |
| 00001008 <__vector_9>: |
| 1008: 1f 92 push r1 |
| 100a: 0f 92 push r0 |
| 100c: 0f b6 in r0, 0x3f ; 63 |
| 100e: 0f 92 push r0 |
| 1010: 11 24 eor r1, r1 |
| 1012: 8f 93 push r24 |
| 1014: 9f 93 push r25 |
| 1016: 80 91 af 02 lds r24, 0x02AF |
| 101a: 8f 5f subi r24, 0xFF ; 255 |
| 101c: 80 93 af 02 sts 0x02AF, r24 |
| 1020: 80 91 9b 00 lds r24, 0x009B |
| 1024: 81 50 subi r24, 0x01 ; 1 |
| 1026: 80 93 9b 00 sts 0x009B, r24 |
| 102a: 8f 3f cpi r24, 0xFF ; 255 |
| 102c: 71 f5 brne .+92 ; 0x108a <__vector_9+0x82> |
| 102e: 83 e0 ldi r24, 0x03 ; 3 |
| 1030: 80 93 9b 00 sts 0x009B, r24 |
| 1034: 80 91 99 00 lds r24, 0x0099 |
| 1038: 90 91 9a 00 lds r25, 0x009A |
| 103c: 01 96 adiw r24, 0x01 ; 1 |
| 103e: 90 93 9a 00 sts 0x009A, r25 |
| 1042: 80 93 99 00 sts 0x0099, r24 |
| 1046: 80 91 81 00 lds r24, 0x0081 |
| 104a: 90 91 82 00 lds r25, 0x0082 |
| 104e: 00 97 sbiw r24, 0x00 ; 0 |
| 1050: 29 f0 breq .+10 ; 0x105c <__vector_9+0x54> |
| 1052: 01 97 sbiw r24, 0x01 ; 1 |
| 1054: 90 93 82 00 sts 0x0082, r25 |
| 1058: 80 93 81 00 sts 0x0081, r24 |
| 105c: 80 91 93 00 lds r24, 0x0093 |
| 1060: 88 23 and r24, r24 |
| 1062: 31 f0 breq .+12 ; 0x1070 <__vector_9+0x68> |
| 1064: 80 91 93 00 lds r24, 0x0093 |
| 1068: 81 50 subi r24, 0x01 ; 1 |
| 106a: 80 93 93 00 sts 0x0093, r24 |
| 106e: 02 c0 rjmp .+4 ; 0x1074 <__vector_9+0x6c> |
| 1070: 10 92 94 00 sts 0x0094, r1 |
| 1074: 80 91 83 00 lds r24, 0x0083 |
| 1078: 90 91 84 00 lds r25, 0x0084 |
| 107c: 00 97 sbiw r24, 0x00 ; 0 |
| 107e: 29 f0 breq .+10 ; 0x108a <__vector_9+0x82> |
| 1080: 01 97 sbiw r24, 0x01 ; 1 |
| 1082: 90 93 84 00 sts 0x0084, r25 |
| 1086: 80 93 83 00 sts 0x0083, r24 |
| 108a: 9f 91 pop r25 |
| 108c: 8f 91 pop r24 |
| 108e: 0f 90 pop r0 |
| 1090: 0f be out 0x3f, r0 ; 63 |
| 1092: 0f 90 pop r0 |
| 1094: 1f 90 pop r1 |
| 1096: 18 95 reti |
| |
| 00001098 <Timer0_Init>: |
| 1098: 82 e0 ldi r24, 0x02 ; 2 |
| 109a: 83 bf out 0x33, r24 ; 51 |
| 109c: 89 b7 in r24, 0x39 ; 57 |
| 109e: 81 60 ori r24, 0x01 ; 1 |
| 10a0: 89 bf out 0x39, r24 ; 57 |
| 10a2: 89 b7 in r24, 0x39 ; 57 |
| 10a4: 80 64 ori r24, 0x40 ; 64 |
| 10a6: 89 bf out 0x39, r24 ; 57 |
| 10a8: 08 95 ret |
| |
| 000010aa <SetDelay>: |
| 10aa: 20 91 99 00 lds r18, 0x0099 |
| 10ae: 30 91 9a 00 lds r19, 0x009A |
| 10b2: 21 50 subi r18, 0x01 ; 1 |
| 10b4: 30 40 sbci r19, 0x00 ; 0 |
| 10b6: 82 0f add r24, r18 |
| 10b8: 93 1f adc r25, r19 |
| 10ba: 08 95 ret |
| |
| 000010bc <CheckDelay>: |
| 10bc: 20 91 99 00 lds r18, 0x0099 |
| 10c0: 30 91 9a 00 lds r19, 0x009A |
| 10c4: 82 1b sub r24, r18 |
| 10c6: 93 0b sbc r25, r19 |
| 10c8: 89 2f mov r24, r25 |
| 10ca: 99 27 eor r25, r25 |
| 10cc: 80 78 andi r24, 0x80 ; 128 |
| 10ce: 99 27 eor r25, r25 |
| 10d0: 08 95 ret |
| |
| 000010d2 <Delay_ms>: |
| 10d2: ac 01 movw r20, r24 |
| 10d4: 20 91 99 00 lds r18, 0x0099 |
| 10d8: 30 91 9a 00 lds r19, 0x009A |
| 10dc: 21 50 subi r18, 0x01 ; 1 |
| 10de: 30 40 sbci r19, 0x00 ; 0 |
| 10e0: 80 91 99 00 lds r24, 0x0099 |
| 10e4: 90 91 9a 00 lds r25, 0x009A |
| 10e8: b9 01 movw r22, r18 |
| 10ea: 68 1b sub r22, r24 |
| 10ec: 79 0b sbc r23, r25 |
| 10ee: cb 01 movw r24, r22 |
| 10f0: 84 0f add r24, r20 |
| 10f2: 95 1f adc r25, r21 |
| 10f4: 80 70 andi r24, 0x00 ; 0 |
| 10f6: 90 78 andi r25, 0x80 ; 128 |
| 10f8: 89 2f mov r24, r25 |
| 10fa: 99 27 eor r25, r25 |
| 10fc: 88 23 and r24, r24 |
| 10fe: 81 f3 breq .-32 ; 0x10e0 <Delay_ms+0xe> |
| 1100: 08 95 ret |
| |
| 00001102 <InitIC2_Slave>: |
| 1102: 90 91 67 00 lds r25, 0x0067 |
| 1106: 99 0f add r25, r25 |
| 1108: 98 0f add r25, r24 |
| 110a: 92 b9 out 0x02, r25 ; 2 |
| 110c: 85 ec ldi r24, 0xC5 ; 197 |
| 110e: 86 bf out 0x36, r24 ; 54 |
| 1110: 08 95 ret |
| |
| 00001112 <__vector_17>: |
| 1112: 1f 92 push r1 |
| 1114: 0f 92 push r0 |
| 1116: 0f b6 in r0, 0x3f ; 63 |
| 1118: 0f 92 push r0 |
| 111a: 11 24 eor r1, r1 |
| 111c: 8f 93 push r24 |
| 111e: 9f 93 push r25 |
| 1120: 81 b1 in r24, 0x01 ; 1 |
| 1122: 99 27 eor r25, r25 |
| 1124: 88 7f andi r24, 0xF8 ; 248 |
| 1126: 90 70 andi r25, 0x00 ; 0 |
| 1128: 80 38 cpi r24, 0x80 ; 128 |
| 112a: 91 05 cpc r25, r1 |
| 112c: c9 f0 breq .+50 ; 0x1160 <__vector_17+0x4e> |
| 112e: 81 38 cpi r24, 0x81 ; 129 |
| 1130: 91 05 cpc r25, r1 |
| 1132: 34 f4 brge .+12 ; 0x1140 <__vector_17+0x2e> |
| 1134: 00 97 sbiw r24, 0x00 ; 0 |
| 1136: 91 f1 breq .+100 ; 0x119c <__vector_17+0x8a> |
| 1138: 80 36 cpi r24, 0x60 ; 96 |
| 113a: 91 05 cpc r25, r1 |
| 113c: 91 f5 brne .+100 ; 0x11a2 <__vector_17+0x90> |
| 113e: 0a c0 rjmp .+20 ; 0x1154 <__vector_17+0x42> |
| 1140: 88 3b cpi r24, 0xB8 ; 184 |
| 1142: 91 05 cpc r25, r1 |
| 1144: b9 f0 breq .+46 ; 0x1174 <__vector_17+0x62> |
| 1146: 88 3f cpi r24, 0xF8 ; 248 |
| 1148: 91 05 cpc r25, r1 |
| 114a: 29 f1 breq .+74 ; 0x1196 <__vector_17+0x84> |
| 114c: 88 3a cpi r24, 0xA8 ; 168 |
| 114e: 91 05 cpc r25, r1 |
| 1150: 41 f5 brne .+80 ; 0x11a2 <__vector_17+0x90> |
| 1152: 10 c0 rjmp .+32 ; 0x1174 <__vector_17+0x62> |
| 1154: 86 b7 in r24, 0x36 ; 54 |
| 1156: 80 68 ori r24, 0x80 ; 128 |
| 1158: 86 bf out 0x36, r24 ; 54 |
| 115a: 10 92 9c 00 sts 0x009C, r1 |
| 115e: 23 c0 rjmp .+70 ; 0x11a6 <__vector_17+0x94> |
| 1160: 83 b1 in r24, 0x03 ; 3 |
| 1162: 80 93 b0 02 sts 0x02B0, r24 |
| 1166: 84 ef ldi r24, 0xF4 ; 244 |
| 1168: 91 e0 ldi r25, 0x01 ; 1 |
| 116a: 90 93 82 00 sts 0x0082, r25 |
| 116e: 80 93 81 00 sts 0x0081, r24 |
| 1172: 0e c0 rjmp .+28 ; 0x1190 <__vector_17+0x7e> |
| 1174: 80 91 9c 00 lds r24, 0x009C |
| 1178: 88 23 and r24, r24 |
| 117a: 39 f4 brne .+14 ; 0x118a <__vector_17+0x78> |
| 117c: 80 91 7e 00 lds r24, 0x007E |
| 1180: 83 b9 out 0x03, r24 ; 3 |
| 1182: 81 e0 ldi r24, 0x01 ; 1 |
| 1184: 80 93 9c 00 sts 0x009C, r24 |
| 1188: 03 c0 rjmp .+6 ; 0x1190 <__vector_17+0x7e> |
| 118a: 80 91 65 00 lds r24, 0x0065 |
| 118e: 83 b9 out 0x03, r24 ; 3 |
| 1190: 86 b7 in r24, 0x36 ; 54 |
| 1192: 80 68 ori r24, 0x80 ; 128 |
| 1194: 07 c0 rjmp .+14 ; 0x11a4 <__vector_17+0x92> |
| 1196: 86 b7 in r24, 0x36 ; 54 |
| 1198: 80 69 ori r24, 0x90 ; 144 |
| 119a: 86 bf out 0x36, r24 ; 54 |
| 119c: 86 b7 in r24, 0x36 ; 54 |
| 119e: 80 69 ori r24, 0x90 ; 144 |
| 11a0: 86 bf out 0x36, r24 ; 54 |
| 11a2: 85 ec ldi r24, 0xC5 ; 197 |
| 11a4: 86 bf out 0x36, r24 ; 54 |
| 11a6: 9f 91 pop r25 |
| 11a8: 8f 91 pop r24 |
| 11aa: 0f 90 pop r0 |
| 11ac: 0f be out 0x3f, r0 ; 63 |
| 11ae: 0f 90 pop r0 |
| 11b0: 1f 90 pop r1 |
| 11b2: 18 95 reti |
| |
| 000011b4 <__vector_13>: |
| 11b4: 1f 92 push r1 |
| 11b6: 0f 92 push r0 |
| 11b8: 0f b6 in r0, 0x3f ; 63 |
| 11ba: 0f 92 push r0 |
| 11bc: 11 24 eor r1, r1 |
| 11be: 0f 90 pop r0 |
| 11c0: 0f be out 0x3f, r0 ; 63 |
| 11c2: 0f 90 pop r0 |
| 11c4: 1f 90 pop r1 |
| 11c6: 18 95 reti |
| |
| 000011c8 <SendUart>: |
| 11c8: 5e 9b sbis 0x0b, 6 ; 11 |
| 11ca: 24 c0 rjmp .+72 ; 0x1214 <SendUart+0x4c> |
| 11cc: 80 91 6e 00 lds r24, 0x006E |
| 11d0: 88 23 and r24, r24 |
| 11d2: e1 f4 brne .+56 ; 0x120c <SendUart+0x44> |
| 11d4: 80 91 ab 00 lds r24, 0x00AB |
| 11d8: 90 91 ac 00 lds r25, 0x00AC |
| 11dc: 01 96 adiw r24, 0x01 ; 1 |
| 11de: 90 93 ac 00 sts 0x00AC, r25 |
| 11e2: 80 93 ab 00 sts 0x00AB, r24 |
| 11e6: fc 01 movw r30, r24 |
| 11e8: ee 54 subi r30, 0x4E ; 78 |
| 11ea: fd 4f sbci r31, 0xFD ; 253 |
| 11ec: e0 81 ld r30, Z |
| 11ee: ed 30 cpi r30, 0x0D ; 13 |
| 11f0: 19 f0 breq .+6 ; 0x11f8 <SendUart+0x30> |
| 11f2: 84 36 cpi r24, 0x64 ; 100 |
| 11f4: 91 05 cpc r25, r1 |
| 11f6: 39 f4 brne .+14 ; 0x1206 <SendUart+0x3e> |
| 11f8: 10 92 ac 00 sts 0x00AC, r1 |
| 11fc: 10 92 ab 00 sts 0x00AB, r1 |
| 1200: 81 e0 ldi r24, 0x01 ; 1 |
| 1202: 80 93 6e 00 sts 0x006E, r24 |
| 1206: 58 9a sbi 0x0b, 0 ; 11 |
| 1208: ec b9 out 0x0c, r30 ; 12 |
| 120a: 08 95 ret |
| 120c: 10 92 ac 00 sts 0x00AC, r1 |
| 1210: 10 92 ab 00 sts 0x00AB, r1 |
| 1214: 08 95 ret |
| |
| 00001216 <Decode64>: |
| { |
| 1216: 1f 93 push r17 |
| 1218: cf 93 push r28 |
| 121a: df 93 push r29 |
| 121c: ec 01 movw r28, r24 |
| 121e: 70 e0 ldi r23, 0x00 ; 0 |
| unsigned char a,b,c,d; |
| unsigned char ptr = 0; |
| unsigned char x,y,z; |
| while(len) |
| { |
| a = RxdBuffer[ptrIn++] - '='; |
| b = RxdBuffer[ptrIn++] - '='; |
| c = RxdBuffer[ptrIn++] - '='; |
| d = RxdBuffer[ptrIn++] - '='; |
| if(ptrIn > max - 2) break; // nicht mehr Daten verarbeiten, als empfangen wurden |
| 1220: a2 2f mov r26, r18 |
| 1222: bb 27 eor r27, r27 |
| 1224: 12 97 sbiw r26, 0x02 ; 2 |
| 1226: 48 c0 rjmp .+144 ; 0x12b8 <Decode64+0xa2> |
| 1228: e4 2f mov r30, r20 |
| 122a: ff 27 eor r31, r31 |
| 122c: e8 5e subi r30, 0xE8 ; 232 |
| 122e: fc 4f sbci r31, 0xFC ; 252 |
| 1230: 30 81 ld r19, Z |
| 1232: 4f 5f subi r20, 0xFF ; 255 |
| 1234: e4 2f mov r30, r20 |
| 1236: ff 27 eor r31, r31 |
| 1238: e8 5e subi r30, 0xE8 ; 232 |
| 123a: fc 4f sbci r31, 0xFC ; 252 |
| 123c: 50 81 ld r21, Z |
| 123e: 4f 5f subi r20, 0xFF ; 255 |
| 1240: e4 2f mov r30, r20 |
| 1242: ff 27 eor r31, r31 |
| 1244: e8 5e subi r30, 0xE8 ; 232 |
| 1246: fc 4f sbci r31, 0xFC ; 252 |
| 1248: 10 81 ld r17, Z |
| 124a: 4f 5f subi r20, 0xFF ; 255 |
| 124c: e4 2f mov r30, r20 |
| 124e: ff 27 eor r31, r31 |
| 1250: e8 5e subi r30, 0xE8 ; 232 |
| 1252: fc 4f sbci r31, 0xFC ; 252 |
| 1254: 20 81 ld r18, Z |
| 1256: 4f 5f subi r20, 0xFF ; 255 |
| 1258: 84 2f mov r24, r20 |
| 125a: 99 27 eor r25, r25 |
| 125c: a8 17 cp r26, r24 |
| 125e: b9 07 cpc r27, r25 |
| 1260: 74 f1 brlt .+92 ; 0x12be <Decode64+0xa8> |
| 1262: 5d 53 subi r21, 0x3D ; 61 |
| |
| x = (a << 2) | (b >> 4); |
| y = ((b & 0x0f) << 4) | (c >> 2); |
| z = ((c & 0x03) << 6) | d; |
| |
| if(len--) ptrOut[ptr++] = x; else break; |
| 1264: fe 01 movw r30, r28 |
| 1266: e7 0f add r30, r23 |
| 1268: f1 1d adc r31, r1 |
| 126a: 85 2f mov r24, r21 |
| 126c: 82 95 swap r24 |
| 126e: 8f 70 andi r24, 0x0F ; 15 |
| 1270: 3d 53 subi r19, 0x3D ; 61 |
| 1272: 33 0f add r19, r19 |
| 1274: 33 0f add r19, r19 |
| 1276: 38 2b or r19, r24 |
| 1278: 30 83 st Z, r19 |
| if(len--) ptrOut[ptr++] = y; else break; |
| 127a: 61 30 cpi r22, 0x01 ; 1 |
| 127c: 01 f1 breq .+64 ; 0x12be <Decode64+0xa8> |
| 127e: 91 2f mov r25, r17 |
| 1280: 9d 53 subi r25, 0x3D ; 61 |
| 1282: 7f 5f subi r23, 0xFF ; 255 |
| 1284: fe 01 movw r30, r28 |
| 1286: e7 0f add r30, r23 |
| 1288: f1 1d adc r31, r1 |
| 128a: 71 50 subi r23, 0x01 ; 1 |
| 128c: 52 95 swap r21 |
| 128e: 50 7f andi r21, 0xF0 ; 240 |
| 1290: 89 2f mov r24, r25 |
| 1292: 86 95 lsr r24 |
| 1294: 86 95 lsr r24 |
| 1296: 58 2b or r21, r24 |
| 1298: 50 83 st Z, r21 |
| 129a: 63 50 subi r22, 0x03 ; 3 |
| if(len--) ptrOut[ptr++] = z; else break; |
| 129c: 6f 3f cpi r22, 0xFF ; 255 |
| 129e: 79 f0 breq .+30 ; 0x12be <Decode64+0xa8> |
| 12a0: 7e 5f subi r23, 0xFE ; 254 |
| 12a2: fe 01 movw r30, r28 |
| 12a4: e7 0f add r30, r23 |
| 12a6: f1 1d adc r31, r1 |
| 12a8: 92 95 swap r25 |
| 12aa: 99 0f add r25, r25 |
| 12ac: 99 0f add r25, r25 |
| 12ae: 90 7c andi r25, 0xC0 ; 192 |
| 12b0: 2d 53 subi r18, 0x3D ; 61 |
| 12b2: 92 2b or r25, r18 |
| 12b4: 90 83 st Z, r25 |
| 12b6: 7f 5f subi r23, 0xFF ; 255 |
| 12b8: 66 23 and r22, r22 |
| 12ba: 09 f0 breq .+2 ; 0x12be <Decode64+0xa8> |
| 12bc: b5 cf rjmp .-150 ; 0x1228 <Decode64+0x12> |
| 12be: df 91 pop r29 |
| 12c0: cf 91 pop r28 |
| 12c2: 1f 91 pop r17 |
| 12c4: 08 95 ret |
| |
| 000012c6 <AddCRC>: |
| } |
| |
| } |
| |
| |
| //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| //++ Empfangs-Part der Datenübertragung |
| //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| SIGNAL(INT_VEC_RX) |
| { |
| |
| #if X3D_SIO == 1 |
| static unsigned char serPacketCounter = 100; |
| SioTmp = UDR; |
| if(SioTmp == 0xF5) // Startzeichen |
| { |
| serPacketCounter = 0; |
| } |
| else |
| { |
| if(++serPacketCounter == MotorAdresse) // (1-4) |
| { |
| SIO_Sollwert = SioTmp; |
| SIO_Timeout = 200; // werte für 200ms gültig |
| } |
| else |
| { |
| if(serPacketCounter > 100) serPacketCounter = 100; |
| } |
| } |
| #else |
| static unsigned int crc; |
| static unsigned char crc1,crc2,buf_ptr; |
| static unsigned char UartState = 0; |
| unsigned char CrcOkay = 0; |
| |
| SioTmp = UDR; |
| if(buf_ptr >= MAX_EMPFANGS_BUFF) UartState = 0; |
| if(SioTmp == '\r' && UartState == 2) |
| { |
| UartState = 0; |
| crc -= RxdBuffer[buf_ptr-2]; |
| crc -= RxdBuffer[buf_ptr-1]; |
| crc %= 4096; |
| crc1 = '=' + crc / 64; |
| crc2 = '=' + crc % 64; |
| CrcOkay = 0; |
| if((crc1 == RxdBuffer[buf_ptr-2]) && (crc2 == RxdBuffer[buf_ptr-1])) CrcOkay = 1; else { CrcOkay = 0; }; |
| if(CrcOkay) // Datensatz schon verarbeitet |
| { |
| //NeuerDatensatzEmpfangen = 1; |
| AnzahlEmpfangsBytes = buf_ptr; |
| |
| RxdBuffer[buf_ptr] = '\r'; |
| if(/*(RxdBuffer[1] == MeineSlaveAdresse || (RxdBuffer[1] == 'a')) && */(RxdBuffer[2] == 'R')) wdt_enable(WDTO_250MS); // Reset-Commando |
| uart_putchar(RxdBuffer[2]); |
| if (RxdBuffer[2] == 't') // Motortest |
| { Decode64((unsigned char *) &MotorTest[0],sizeof(MotorTest),3,AnzahlEmpfangsBytes); |
| SIO_Sollwert = MotorTest[MotorAdresse - 1]; |
| SIO_Timeout = 500; // werte für 500ms gültig |
| |
| } |
| } |
| } |
| else |
| switch(UartState) |
| { |
| case 0: |
| if(SioTmp == '#' && !NeuerDatensatzEmpfangen) UartState = 1; // Startzeichen und Daten schon verarbeitet |
| buf_ptr = 0; |
| RxdBuffer[buf_ptr++] = SioTmp; |
| crc = SioTmp; |
| break; |
| case 1: // Adresse auswerten |
| UartState++; |
| RxdBuffer[buf_ptr++] = SioTmp; |
| crc += SioTmp; |
| break; |
| case 2: // Eingangsdaten sammeln |
| RxdBuffer[buf_ptr] = SioTmp; |
| if(buf_ptr < MAX_EMPFANGS_BUFF) buf_ptr++; |
| else UartState = 0; |
| crc += SioTmp; |
| break; |
| default: |
| UartState = 0; |
| break; |
| } |
| |
| |
| #endif |
| }; |
| |
| |
| // -------------------------------------------------------------------------- |
| void AddCRC(unsigned int wieviele) |
| { |
| 12c6: dc 01 movw r26, r24 |
| 12c8: 20 e0 ldi r18, 0x00 ; 0 |
| 12ca: 30 e0 ldi r19, 0x00 ; 0 |
| 12cc: 40 e0 ldi r20, 0x00 ; 0 |
| 12ce: 50 e0 ldi r21, 0x00 ; 0 |
| 12d0: 08 c0 rjmp .+16 ; 0x12e2 <AddCRC+0x1c> |
| unsigned int tmpCRC = 0,i; |
| for(i = 0; i < wieviele;i++) |
| { |
| tmpCRC += SendeBuffer[i]; |
| 12d2: fa 01 movw r30, r20 |
| 12d4: ee 54 subi r30, 0x4E ; 78 |
| 12d6: fd 4f sbci r31, 0xFD ; 253 |
| 12d8: 80 81 ld r24, Z |
| 12da: 28 0f add r18, r24 |
| 12dc: 31 1d adc r19, r1 |
| 12de: 4f 5f subi r20, 0xFF ; 255 |
| 12e0: 5f 4f sbci r21, 0xFF ; 255 |
| 12e2: 4a 17 cp r20, r26 |
| 12e4: 5b 07 cpc r21, r27 |
| 12e6: a9 f7 brne .-22 ; 0x12d2 <AddCRC+0xc> |
| } |
| tmpCRC %= 4096; |
| 12e8: 3f 70 andi r19, 0x0F ; 15 |
| SendeBuffer[i++] = '=' + tmpCRC / 64; |
| 12ea: c9 01 movw r24, r18 |
| 12ec: 36 e0 ldi r19, 0x06 ; 6 |
| 12ee: 96 95 lsr r25 |
| 12f0: 87 95 ror r24 |
| 12f2: 3a 95 dec r19 |
| 12f4: e1 f7 brne .-8 ; 0x12ee <AddCRC+0x28> |
| 12f6: 83 5c subi r24, 0xC3 ; 195 |
| 12f8: fd 01 movw r30, r26 |
| 12fa: ee 54 subi r30, 0x4E ; 78 |
| 12fc: fd 4f sbci r31, 0xFD ; 253 |
| 12fe: 80 83 st Z, r24 |
| 1300: 11 96 adiw r26, 0x01 ; 1 |
| SendeBuffer[i++] = '=' + tmpCRC % 64; |
| 1302: 2f 73 andi r18, 0x3F ; 63 |
| 1304: 23 5c subi r18, 0xC3 ; 195 |
| 1306: fd 01 movw r30, r26 |
| 1308: ee 54 subi r30, 0x4E ; 78 |
| 130a: fd 4f sbci r31, 0xFD ; 253 |
| 130c: 20 83 st Z, r18 |
| SendeBuffer[i++] = '\r'; |
| 130e: ad 54 subi r26, 0x4D ; 77 |
| 1310: bd 4f sbci r27, 0xFD ; 253 |
| 1312: 8d e0 ldi r24, 0x0D ; 13 |
| 1314: 8c 93 st X, r24 |
| UebertragungAbgeschlossen = 0; |
| 1316: 10 92 6e 00 sts 0x006E, r1 |
| UDR = SendeBuffer[0]; |
| 131a: 80 91 b2 02 lds r24, 0x02B2 |
| 131e: 8c b9 out 0x0c, r24 ; 12 |
| 1320: 08 95 ret |
| |
| 00001322 <SendOutData>: |
| } |
| |
| |
| // -------------------------------------------------------------------------- |
| void SendOutData(unsigned char cmd,unsigned char modul, unsigned char *snd, unsigned char len) |
| { |
| 1322: 1f 93 push r17 |
| 1324: cf 93 push r28 |
| 1326: df 93 push r29 |
| 1328: ea 01 movw r28, r20 |
| 132a: 72 2f mov r23, r18 |
| unsigned int pt = 0; |
| unsigned char a,b,c; |
| unsigned char ptr = 0; |
| |
| |
| SendeBuffer[pt++] = '#'; // Startzeichen |
| 132c: 93 e2 ldi r25, 0x23 ; 35 |
| 132e: 90 93 b2 02 sts 0x02B2, r25 |
| SendeBuffer[pt++] = modul; // Adresse (a=0; b=1,...) |
| 1332: 60 93 b3 02 sts 0x02B3, r22 |
| SendeBuffer[pt++] = cmd; // Commando |
| 1336: 80 93 b4 02 sts 0x02B4, r24 |
| 133a: a3 e0 ldi r26, 0x03 ; 3 |
| 133c: b0 e0 ldi r27, 0x00 ; 0 |
| 133e: 60 e0 ldi r22, 0x00 ; 0 |
| 1340: 4f c0 rjmp .+158 ; 0x13e0 <SendOutData+0xbe> |
| |
| while(len) |
| { |
| if(len) { a = snd[ptr++]; len--;} else a = 0; |
| 1342: fe 01 movw r30, r28 |
| 1344: e6 0f add r30, r22 |
| 1346: f1 1d adc r31, r1 |
| 1348: 90 81 ld r25, Z |
| 134a: 6f 5f subi r22, 0xFF ; 255 |
| 134c: 71 50 subi r23, 0x01 ; 1 |
| if(len) { b = snd[ptr++]; len--;} else b = 0; |
| 134e: 19 f4 brne .+6 ; 0x1356 <SendOutData+0x34> |
| 1350: 10 e0 ldi r17, 0x00 ; 0 |
| 1352: 40 e0 ldi r20, 0x00 ; 0 |
| 1354: 0f c0 rjmp .+30 ; 0x1374 <SendOutData+0x52> |
| 1356: fe 01 movw r30, r28 |
| 1358: e6 0f add r30, r22 |
| 135a: f1 1d adc r31, r1 |
| 135c: 40 81 ld r20, Z |
| 135e: 6f 5f subi r22, 0xFF ; 255 |
| 1360: 71 50 subi r23, 0x01 ; 1 |
| if(len) { c = snd[ptr++]; len--;} else c = 0; |
| 1362: 11 f4 brne .+4 ; 0x1368 <SendOutData+0x46> |
| 1364: 10 e0 ldi r17, 0x00 ; 0 |
| 1366: 06 c0 rjmp .+12 ; 0x1374 <SendOutData+0x52> |
| 1368: fe 01 movw r30, r28 |
| 136a: e6 0f add r30, r22 |
| 136c: f1 1d adc r31, r1 |
| 136e: 10 81 ld r17, Z |
| 1370: 6f 5f subi r22, 0xFF ; 255 |
| 1372: 71 50 subi r23, 0x01 ; 1 |
| SendeBuffer[pt++] = '=' + (a >> 2); |
| 1374: 89 2f mov r24, r25 |
| 1376: 86 95 lsr r24 |
| 1378: 86 95 lsr r24 |
| 137a: 83 5c subi r24, 0xC3 ; 195 |
| 137c: fd 01 movw r30, r26 |
| 137e: ee 54 subi r30, 0x4E ; 78 |
| 1380: fd 4f sbci r31, 0xFD ; 253 |
| 1382: 80 83 st Z, r24 |
| SendeBuffer[pt++] = '=' + (((a & 0x03) << 4) | ((b & 0xf0) >> 4)); |
| 1384: 55 27 eor r21, r21 |
| 1386: 9a 01 movw r18, r20 |
| 1388: 84 e0 ldi r24, 0x04 ; 4 |
| 138a: 36 95 lsr r19 |
| 138c: 27 95 ror r18 |
| 138e: 8a 95 dec r24 |
| 1390: e1 f7 brne .-8 ; 0x138a <SendOutData+0x68> |
| 1392: 89 2f mov r24, r25 |
| 1394: 99 27 eor r25, r25 |
| 1396: 83 70 andi r24, 0x03 ; 3 |
| 1398: 90 70 andi r25, 0x00 ; 0 |
| 139a: f4 e0 ldi r31, 0x04 ; 4 |
| 139c: 88 0f add r24, r24 |
| 139e: 99 1f adc r25, r25 |
| 13a0: fa 95 dec r31 |
| 13a2: e1 f7 brne .-8 ; 0x139c <SendOutData+0x7a> |
| 13a4: 28 2b or r18, r24 |
| 13a6: 23 5c subi r18, 0xC3 ; 195 |
| 13a8: fd 01 movw r30, r26 |
| 13aa: ed 54 subi r30, 0x4D ; 77 |
| 13ac: fd 4f sbci r31, 0xFD ; 253 |
| 13ae: 20 83 st Z, r18 |
| SendeBuffer[pt++] = '=' + (((b & 0x0f) << 2) | ((c & 0xc0) >> 6)); |
| 13b0: 81 2f mov r24, r17 |
| 13b2: 82 95 swap r24 |
| 13b4: 86 95 lsr r24 |
| 13b6: 86 95 lsr r24 |
| 13b8: 83 70 andi r24, 0x03 ; 3 |
| 13ba: 4f 70 andi r20, 0x0F ; 15 |
| 13bc: 50 70 andi r21, 0x00 ; 0 |
| 13be: 44 0f add r20, r20 |
| 13c0: 55 1f adc r21, r21 |
| 13c2: 44 0f add r20, r20 |
| 13c4: 55 1f adc r21, r21 |
| 13c6: 84 2b or r24, r20 |
| 13c8: 83 5c subi r24, 0xC3 ; 195 |
| 13ca: fd 01 movw r30, r26 |
| 13cc: ec 54 subi r30, 0x4C ; 76 |
| 13ce: fd 4f sbci r31, 0xFD ; 253 |
| 13d0: 80 83 st Z, r24 |
| SendeBuffer[pt++] = '=' + ( c & 0x3f); |
| 13d2: 1f 73 andi r17, 0x3F ; 63 |
| 13d4: 13 5c subi r17, 0xC3 ; 195 |
| 13d6: fd 01 movw r30, r26 |
| 13d8: eb 54 subi r30, 0x4B ; 75 |
| 13da: fd 4f sbci r31, 0xFD ; 253 |
| 13dc: 10 83 st Z, r17 |
| 13de: 14 96 adiw r26, 0x04 ; 4 |
| 13e0: 77 23 and r23, r23 |
| 13e2: 09 f0 breq .+2 ; 0x13e6 <SendOutData+0xc4> |
| 13e4: ae cf rjmp .-164 ; 0x1342 <SendOutData+0x20> |
| } |
| AddCRC(pt); |
| 13e6: cd 01 movw r24, r26 |
| 13e8: 6e df rcall .-292 ; 0x12c6 <AddCRC> |
| 13ea: df 91 pop r29 |
| 13ec: cf 91 pop r28 |
| 13ee: 1f 91 pop r17 |
| 13f0: 08 95 ret |
| |
| 000013f2 <uart_putchar>: |
| } |
| |
| |
| |
| //############################################################################ |
| //Routine für die Serielle Ausgabe |
| int uart_putchar (char c) |
| //############################################################################ |
| { |
| 13f2: 1f 93 push r17 |
| 13f4: 18 2f mov r17, r24 |
| if (c == '\n') |
| 13f6: 8a 30 cpi r24, 0x0A ; 10 |
| 13f8: 11 f4 brne .+4 ; 0x13fe <uart_putchar+0xc> |
| uart_putchar('\r'); |
| 13fa: 8d e0 ldi r24, 0x0D ; 13 |
| 13fc: fa df rcall .-12 ; 0x13f2 <uart_putchar> |
| //Warten solange bis Zeichen gesendet wurde |
| loop_until_bit_is_set(USR, UDRE); |
| 13fe: 5d 9b sbis 0x0b, 5 ; 11 |
| 1400: fe cf rjmp .-4 ; 0x13fe <uart_putchar+0xc> |
| //Ausgabe des Zeichens |
| UDR = c; |
| 1402: 1c b9 out 0x0c, r17 ; 12 |
| |
| return (0); |
| } |
| 1404: 80 e0 ldi r24, 0x00 ; 0 |
| 1406: 90 e0 ldi r25, 0x00 ; 0 |
| 1408: 1f 91 pop r17 |
| 140a: 08 95 ret |
| |
| 0000140c <__vector_11>: |
| 140c: 1f 92 push r1 |
| 140e: 0f 92 push r0 |
| 1410: 0f b6 in r0, 0x3f ; 63 |
| 1412: 0f 92 push r0 |
| 1414: 11 24 eor r1, r1 |
| 1416: 2f 93 push r18 |
| 1418: 3f 93 push r19 |
| 141a: 4f 93 push r20 |
| 141c: 5f 93 push r21 |
| 141e: 6f 93 push r22 |
| 1420: 7f 93 push r23 |
| 1422: 8f 93 push r24 |
| 1424: 9f 93 push r25 |
| 1426: af 93 push r26 |
| 1428: bf 93 push r27 |
| 142a: cf 93 push r28 |
| 142c: df 93 push r29 |
| 142e: ef 93 push r30 |
| 1430: ff 93 push r31 |
| 1432: 8c b1 in r24, 0x0c ; 12 |
| 1434: 80 93 9e 00 sts 0x009E, r24 |
| 1438: 40 91 a6 00 lds r20, 0x00A6 |
| 143c: 44 36 cpi r20, 0x64 ; 100 |
| 143e: 10 f0 brcs .+4 ; 0x1444 <__vector_11+0x38> |
| 1440: 10 92 a5 00 sts 0x00A5, r1 |
| 1444: 50 91 9e 00 lds r21, 0x009E |
| 1448: 5d 30 cpi r21, 0x0D ; 13 |
| 144a: 09 f0 breq .+2 ; 0x144e <__vector_11+0x42> |
| 144c: 64 c0 rjmp .+200 ; 0x1516 <__vector_11+0x10a> |
| 144e: 80 91 a5 00 lds r24, 0x00A5 |
| 1452: 82 30 cpi r24, 0x02 ; 2 |
| 1454: 09 f0 breq .+2 ; 0x1458 <__vector_11+0x4c> |
| 1456: 5f c0 rjmp .+190 ; 0x1516 <__vector_11+0x10a> |
| 1458: 10 92 a5 00 sts 0x00A5, r1 |
| 145c: a4 2f mov r26, r20 |
| 145e: bb 27 eor r27, r27 |
| 1460: fd 01 movw r30, r26 |
| 1462: ea 5e subi r30, 0xEA ; 234 |
| 1464: fc 4f sbci r31, 0xFC ; 252 |
| 1466: 30 81 ld r19, Z |
| 1468: ed 01 movw r28, r26 |
| 146a: c9 5e subi r28, 0xE9 ; 233 |
| 146c: dc 4f sbci r29, 0xFC ; 252 |
| 146e: 28 81 ld r18, Y |
| 1470: 80 91 a9 00 lds r24, 0x00A9 |
| 1474: 90 91 aa 00 lds r25, 0x00AA |
| 1478: 83 1b sub r24, r19 |
| 147a: 91 09 sbc r25, r1 |
| 147c: 82 1b sub r24, r18 |
| 147e: 91 09 sbc r25, r1 |
| 1480: 9f 70 andi r25, 0x0F ; 15 |
| 1482: 90 93 aa 00 sts 0x00AA, r25 |
| 1486: 80 93 a9 00 sts 0x00A9, r24 |
| 148a: 9c 01 movw r18, r24 |
| 148c: 96 e0 ldi r25, 0x06 ; 6 |
| 148e: 36 95 lsr r19 |
| 1490: 27 95 ror r18 |
| 1492: 9a 95 dec r25 |
| 1494: e1 f7 brne .-8 ; 0x148e <__vector_11+0x82> |
| 1496: 23 5c subi r18, 0xC3 ; 195 |
| 1498: 20 93 a8 00 sts 0x00A8, r18 |
| 149c: 98 2f mov r25, r24 |
| 149e: 9f 73 andi r25, 0x3F ; 63 |
| 14a0: 93 5c subi r25, 0xC3 ; 195 |
| 14a2: 90 93 a7 00 sts 0x00A7, r25 |
| 14a6: 80 81 ld r24, Z |
| 14a8: 28 17 cp r18, r24 |
| 14aa: 09 f0 breq .+2 ; 0x14ae <__vector_11+0xa2> |
| 14ac: 7c c0 rjmp .+248 ; 0x15a6 <__vector_11+0x19a> |
| 14ae: 88 81 ld r24, Y |
| 14b0: 98 17 cp r25, r24 |
| 14b2: 09 f0 breq .+2 ; 0x14b6 <__vector_11+0xaa> |
| 14b4: 78 c0 rjmp .+240 ; 0x15a6 <__vector_11+0x19a> |
| 14b6: 40 93 a4 00 sts 0x00A4, r20 |
| 14ba: a8 5e subi r26, 0xE8 ; 232 |
| 14bc: bc 4f sbci r27, 0xFC ; 252 |
| 14be: 5c 93 st X, r21 |
| 14c0: 80 91 1a 03 lds r24, 0x031A |
| 14c4: 82 35 cpi r24, 0x52 ; 82 |
| 14c6: 49 f4 brne .+18 ; 0x14da <__vector_11+0xce> |
| 14c8: 88 e1 ldi r24, 0x18 ; 24 |
| 14ca: 90 e0 ldi r25, 0x00 ; 0 |
| 14cc: 2c e0 ldi r18, 0x0C ; 12 |
| 14ce: 0f b6 in r0, 0x3f ; 63 |
| 14d0: f8 94 cli |
| 14d2: a8 95 wdr |
| 14d4: 81 bd out 0x21, r24 ; 33 |
| 14d6: 0f be out 0x3f, r0 ; 63 |
| 14d8: 21 bd out 0x21, r18 ; 33 |
| 14da: 80 91 1a 03 lds r24, 0x031A |
| 14de: 89 df rcall .-238 ; 0x13f2 <uart_putchar> |
| 14e0: 80 91 1a 03 lds r24, 0x031A |
| 14e4: 84 37 cpi r24, 0x74 ; 116 |
| 14e6: 09 f0 breq .+2 ; 0x14ea <__vector_11+0xde> |
| 14e8: 5e c0 rjmp .+188 ; 0x15a6 <__vector_11+0x19a> |
| 14ea: 20 91 a4 00 lds r18, 0x00A4 |
| 14ee: 43 e0 ldi r20, 0x03 ; 3 |
| 14f0: 64 e0 ldi r22, 0x04 ; 4 |
| 14f2: 80 ea ldi r24, 0xA0 ; 160 |
| 14f4: 90 e0 ldi r25, 0x00 ; 0 |
| 14f6: 8f de rcall .-738 ; 0x1216 <Decode64> |
| 14f8: e0 91 67 00 lds r30, 0x0067 |
| 14fc: ff 27 eor r31, r31 |
| 14fe: e1 56 subi r30, 0x61 ; 97 |
| 1500: ff 4f sbci r31, 0xFF ; 255 |
| 1502: 80 81 ld r24, Z |
| 1504: 80 93 9d 00 sts 0x009D, r24 |
| 1508: 84 ef ldi r24, 0xF4 ; 244 |
| 150a: 91 e0 ldi r25, 0x01 ; 1 |
| 150c: 90 93 84 00 sts 0x0084, r25 |
| 1510: 80 93 83 00 sts 0x0083, r24 |
| 1514: 48 c0 rjmp .+144 ; 0x15a6 <__vector_11+0x19a> |
| 1516: 80 91 a5 00 lds r24, 0x00A5 |
| 151a: 81 30 cpi r24, 0x01 ; 1 |
| 151c: d9 f0 breq .+54 ; 0x1554 <__vector_11+0x148> |
| 151e: 81 30 cpi r24, 0x01 ; 1 |
| 1520: 18 f0 brcs .+6 ; 0x1528 <__vector_11+0x11c> |
| 1522: 82 30 cpi r24, 0x02 ; 2 |
| 1524: f1 f5 brne .+124 ; 0x15a2 <__vector_11+0x196> |
| 1526: 21 c0 rjmp .+66 ; 0x156a <__vector_11+0x15e> |
| 1528: 80 91 9e 00 lds r24, 0x009E |
| 152c: 83 32 cpi r24, 0x23 ; 35 |
| 152e: 39 f4 brne .+14 ; 0x153e <__vector_11+0x132> |
| 1530: 80 91 9f 00 lds r24, 0x009F |
| 1534: 88 23 and r24, r24 |
| 1536: 19 f4 brne .+6 ; 0x153e <__vector_11+0x132> |
| 1538: 81 e0 ldi r24, 0x01 ; 1 |
| 153a: 80 93 a5 00 sts 0x00A5, r24 |
| 153e: 80 91 9e 00 lds r24, 0x009E |
| 1542: 80 93 18 03 sts 0x0318, r24 |
| 1546: 81 e0 ldi r24, 0x01 ; 1 |
| 1548: 80 93 a6 00 sts 0x00A6, r24 |
| 154c: 80 91 9e 00 lds r24, 0x009E |
| 1550: 99 27 eor r25, r25 |
| 1552: 22 c0 rjmp .+68 ; 0x1598 <__vector_11+0x18c> |
| 1554: 82 e0 ldi r24, 0x02 ; 2 |
| 1556: 80 93 a5 00 sts 0x00A5, r24 |
| 155a: e4 2f mov r30, r20 |
| 155c: ff 27 eor r31, r31 |
| 155e: 80 91 9e 00 lds r24, 0x009E |
| 1562: e8 5e subi r30, 0xE8 ; 232 |
| 1564: fc 4f sbci r31, 0xFC ; 252 |
| 1566: 80 83 st Z, r24 |
| 1568: 09 c0 rjmp .+18 ; 0x157c <__vector_11+0x170> |
| 156a: e4 2f mov r30, r20 |
| 156c: ff 27 eor r31, r31 |
| 156e: 80 91 9e 00 lds r24, 0x009E |
| 1572: e8 5e subi r30, 0xE8 ; 232 |
| 1574: fc 4f sbci r31, 0xFC ; 252 |
| 1576: 80 83 st Z, r24 |
| 1578: 44 36 cpi r20, 0x64 ; 100 |
| 157a: 20 f4 brcc .+8 ; 0x1584 <__vector_11+0x178> |
| 157c: 4f 5f subi r20, 0xFF ; 255 |
| 157e: 40 93 a6 00 sts 0x00A6, r20 |
| 1582: 02 c0 rjmp .+4 ; 0x1588 <__vector_11+0x17c> |
| 1584: 10 92 a5 00 sts 0x00A5, r1 |
| 1588: 20 91 9e 00 lds r18, 0x009E |
| 158c: 80 91 a9 00 lds r24, 0x00A9 |
| 1590: 90 91 aa 00 lds r25, 0x00AA |
| 1594: 82 0f add r24, r18 |
| 1596: 91 1d adc r25, r1 |
| 1598: 90 93 aa 00 sts 0x00AA, r25 |
| 159c: 80 93 a9 00 sts 0x00A9, r24 |
| 15a0: 02 c0 rjmp .+4 ; 0x15a6 <__vector_11+0x19a> |
| 15a2: 10 92 a5 00 sts 0x00A5, r1 |
| 15a6: ff 91 pop r31 |
| 15a8: ef 91 pop r30 |
| 15aa: df 91 pop r29 |
| 15ac: cf 91 pop r28 |
| 15ae: bf 91 pop r27 |
| 15b0: af 91 pop r26 |
| 15b2: 9f 91 pop r25 |
| 15b4: 8f 91 pop r24 |
| 15b6: 7f 91 pop r23 |
| 15b8: 6f 91 pop r22 |
| 15ba: 5f 91 pop r21 |
| 15bc: 4f 91 pop r20 |
| 15be: 3f 91 pop r19 |
| 15c0: 2f 91 pop r18 |
| 15c2: 0f 90 pop r0 |
| 15c4: 0f be out 0x3f, r0 ; 63 |
| 15c6: 0f 90 pop r0 |
| 15c8: 1f 90 pop r1 |
| 15ca: 18 95 reti |
| |
| 000015cc <WriteProgramData>: |
| |
| // -------------------------------------------------------------------------- |
| void WriteProgramData(unsigned int pos, unsigned char wert) |
| { |
| 15cc: 08 95 ret |
| |
| 000015ce <DatenUebertragung>: |
| } |
| |
| //############################################################################ |
| //INstallation der Seriellen Schnittstelle |
| void UART_Init (void) |
| //############################################################################ |
| { |
| //Enable TXEN im Register UCR TX-Data Enable & RX Enable |
| |
| UCR=(1 << TXEN) | (1 << RXEN); |
| // UART Double Speed (U2X) |
| USR |= (1<<U2X); |
| // RX-Interrupt Freigabe |
| |
| UCSRB |= (1<<RXCIE); // serieller Empfangsinterrupt |
| |
| // TX-Interrupt Freigabe |
| // UCSRB |= (1<<TXCIE); |
| |
| //Teiler wird gesetzt |
| UBRR= (SYSCLK / (BAUD_RATE * 8L) -1 ); |
| //öffnet einen Kanal für printf (STDOUT) |
| fdevopen (uart_putchar, NULL); |
| Debug_Timer = SetDelay(200); |
| // Version beim Start ausgeben (nicht schön, aber geht... ) |
| uart_putchar ('\n');uart_putchar ('B');uart_putchar ('L');uart_putchar (':'); |
| uart_putchar ('V');uart_putchar (0x30 + VERSION_HAUPTVERSION);uart_putchar ('.');uart_putchar (0x30 + VERSION_NEBENVERSION/10); uart_putchar (0x30 + VERSION_NEBENVERSION%10); |
| uart_putchar ('\n');uart_putchar ('A');uart_putchar ('D');uart_putchar ('R'); uart_putchar (':'); uart_putchar (0x30 + MotorAdresse); |
| |
| } |
| |
| |
| |
| |
| //--------------------------------------------------------------------------------------------- |
| void DatenUebertragung(void) |
| { |
| if((CheckDelay(Debug_Timer) && UebertragungAbgeschlossen)) // im Singlestep-Betrieb in jedem Schtitt senden |
| 15ce: 80 91 16 03 lds r24, 0x0316 |
| 15d2: 90 91 17 03 lds r25, 0x0317 |
| 15d6: 72 dd rcall .-1308 ; 0x10bc <CheckDelay> |
| 15d8: 88 23 and r24, r24 |
| 15da: 91 f0 breq .+36 ; 0x1600 <DatenUebertragung+0x32> |
| 15dc: 80 91 6e 00 lds r24, 0x006E |
| 15e0: 88 23 and r24, r24 |
| 15e2: 71 f0 breq .+28 ; 0x1600 <DatenUebertragung+0x32> |
| { |
| SendOutData('D',MeineSlaveAdresse,(unsigned char *) &DebugOut,sizeof(DebugOut)); |
| 15e4: 60 91 b1 02 lds r22, 0x02B1 |
| 15e8: 22 e2 ldi r18, 0x22 ; 34 |
| 15ea: 4c e7 ldi r20, 0x7C ; 124 |
| 15ec: 53 e0 ldi r21, 0x03 ; 3 |
| 15ee: 84 e4 ldi r24, 0x44 ; 68 |
| 15f0: 98 de rcall .-720 ; 0x1322 <SendOutData> |
| Debug_Timer = SetDelay(50); // Sendeintervall |
| 15f2: 82 e3 ldi r24, 0x32 ; 50 |
| 15f4: 90 e0 ldi r25, 0x00 ; 0 |
| 15f6: 59 dd rcall .-1358 ; 0x10aa <SetDelay> |
| 15f8: 90 93 17 03 sts 0x0317, r25 |
| 15fc: 80 93 16 03 sts 0x0316, r24 |
| 1600: 08 95 ret |
| |
| 00001602 <UART_Init>: |
| 1602: 88 e1 ldi r24, 0x18 ; 24 |
| 1604: 8a b9 out 0x0a, r24 ; 10 |
| 1606: 59 9a sbi 0x0b, 1 ; 11 |
| 1608: 57 9a sbi 0x0a, 7 ; 10 |
| 160a: 80 e1 ldi r24, 0x10 ; 16 |
| 160c: 89 b9 out 0x09, r24 ; 9 |
| 160e: 60 e0 ldi r22, 0x00 ; 0 |
| 1610: 70 e0 ldi r23, 0x00 ; 0 |
| 1612: 89 ef ldi r24, 0xF9 ; 249 |
| 1614: 99 e0 ldi r25, 0x09 ; 9 |
| 1616: 28 d0 rcall .+80 ; 0x1668 <fdevopen> |
| 1618: 88 ec ldi r24, 0xC8 ; 200 |
| 161a: 90 e0 ldi r25, 0x00 ; 0 |
| 161c: 46 dd rcall .-1396 ; 0x10aa <SetDelay> |
| 161e: 90 93 17 03 sts 0x0317, r25 |
| 1622: 80 93 16 03 sts 0x0316, r24 |
| 1626: 8a e0 ldi r24, 0x0A ; 10 |
| 1628: e4 de rcall .-568 ; 0x13f2 <uart_putchar> |
| 162a: 82 e4 ldi r24, 0x42 ; 66 |
| 162c: e2 de rcall .-572 ; 0x13f2 <uart_putchar> |
| 162e: 8c e4 ldi r24, 0x4C ; 76 |
| 1630: e0 de rcall .-576 ; 0x13f2 <uart_putchar> |
| 1632: 8a e3 ldi r24, 0x3A ; 58 |
| 1634: de de rcall .-580 ; 0x13f2 <uart_putchar> |
| 1636: 86 e5 ldi r24, 0x56 ; 86 |
| 1638: dc de rcall .-584 ; 0x13f2 <uart_putchar> |
| 163a: 80 e3 ldi r24, 0x30 ; 48 |
| 163c: da de rcall .-588 ; 0x13f2 <uart_putchar> |
| 163e: 8e e2 ldi r24, 0x2E ; 46 |
| 1640: d8 de rcall .-592 ; 0x13f2 <uart_putchar> |
| 1642: 83 e3 ldi r24, 0x33 ; 51 |
| 1644: d6 de rcall .-596 ; 0x13f2 <uart_putchar> |
| 1646: 87 e3 ldi r24, 0x37 ; 55 |
| 1648: d4 de rcall .-600 ; 0x13f2 <uart_putchar> |
| 164a: 8a e0 ldi r24, 0x0A ; 10 |
| 164c: d2 de rcall .-604 ; 0x13f2 <uart_putchar> |
| 164e: 81 e4 ldi r24, 0x41 ; 65 |
| 1650: d0 de rcall .-608 ; 0x13f2 <uart_putchar> |
| 1652: 84 e4 ldi r24, 0x44 ; 68 |
| 1654: ce de rcall .-612 ; 0x13f2 <uart_putchar> |
| 1656: 82 e5 ldi r24, 0x52 ; 82 |
| 1658: cc de rcall .-616 ; 0x13f2 <uart_putchar> |
| 165a: 8a e3 ldi r24, 0x3A ; 58 |
| 165c: ca de rcall .-620 ; 0x13f2 <uart_putchar> |
| 165e: 80 91 67 00 lds r24, 0x0067 |
| 1662: 80 5d subi r24, 0xD0 ; 208 |
| 1664: c6 de rcall .-628 ; 0x13f2 <uart_putchar> |
| 1666: 08 95 ret |
| |
| 00001668 <fdevopen>: |
| 1668: ef 92 push r14 |
| 166a: ff 92 push r15 |
| 166c: 0f 93 push r16 |
| 166e: 1f 93 push r17 |
| 1670: cf 93 push r28 |
| 1672: df 93 push r29 |
| 1674: 8c 01 movw r16, r24 |
| 1676: 7b 01 movw r14, r22 |
| 1678: 89 2b or r24, r25 |
| 167a: 11 f4 brne .+4 ; 0x1680 <fdevopen+0x18> |
| 167c: 67 2b or r22, r23 |
| 167e: c9 f1 breq .+114 ; 0x16f2 <fdevopen+0x8a> |
| 1680: 6e e0 ldi r22, 0x0E ; 14 |
| 1682: 70 e0 ldi r23, 0x00 ; 0 |
| 1684: 81 e0 ldi r24, 0x01 ; 1 |
| 1686: 90 e0 ldi r25, 0x00 ; 0 |
| 1688: 3b d0 rcall .+118 ; 0x1700 <calloc> |
| 168a: fc 01 movw r30, r24 |
| 168c: 00 97 sbiw r24, 0x00 ; 0 |
| 168e: 89 f1 breq .+98 ; 0x16f2 <fdevopen+0x8a> |
| 1690: dc 01 movw r26, r24 |
| 1692: 80 e8 ldi r24, 0x80 ; 128 |
| 1694: 83 83 std Z+3, r24 ; 0x03 |
| 1696: e1 14 cp r14, r1 |
| 1698: f1 04 cpc r15, r1 |
| 169a: 71 f0 breq .+28 ; 0x16b8 <fdevopen+0x50> |
| 169c: f3 86 std Z+11, r15 ; 0x0b |
| 169e: e2 86 std Z+10, r14 ; 0x0a |
| 16a0: 81 e8 ldi r24, 0x81 ; 129 |
| 16a2: 83 83 std Z+3, r24 ; 0x03 |
| 16a4: 80 91 9e 03 lds r24, 0x039E |
| 16a8: 90 91 9f 03 lds r25, 0x039F |
| 16ac: 89 2b or r24, r25 |
| 16ae: 21 f4 brne .+8 ; 0x16b8 <fdevopen+0x50> |
| 16b0: f0 93 9f 03 sts 0x039F, r31 |
| 16b4: e0 93 9e 03 sts 0x039E, r30 |
| 16b8: 01 15 cp r16, r1 |
| 16ba: 11 05 cpc r17, r1 |
| 16bc: e1 f0 breq .+56 ; 0x16f6 <fdevopen+0x8e> |
| 16be: 11 87 std Z+9, r17 ; 0x09 |
| 16c0: 00 87 std Z+8, r16 ; 0x08 |
| 16c2: 83 81 ldd r24, Z+3 ; 0x03 |
| 16c4: 82 60 ori r24, 0x02 ; 2 |
| 16c6: 83 83 std Z+3, r24 ; 0x03 |
| 16c8: 80 91 a0 03 lds r24, 0x03A0 |
| 16cc: 90 91 a1 03 lds r25, 0x03A1 |
| 16d0: 89 2b or r24, r25 |
| 16d2: 89 f4 brne .+34 ; 0x16f6 <fdevopen+0x8e> |
| 16d4: f0 93 a1 03 sts 0x03A1, r31 |
| 16d8: e0 93 a0 03 sts 0x03A0, r30 |
| 16dc: 80 91 a2 03 lds r24, 0x03A2 |
| 16e0: 90 91 a3 03 lds r25, 0x03A3 |
| 16e4: 89 2b or r24, r25 |
| 16e6: 39 f4 brne .+14 ; 0x16f6 <fdevopen+0x8e> |
| 16e8: f0 93 a3 03 sts 0x03A3, r31 |
| 16ec: e0 93 a2 03 sts 0x03A2, r30 |
| 16f0: 02 c0 rjmp .+4 ; 0x16f6 <fdevopen+0x8e> |
| 16f2: a0 e0 ldi r26, 0x00 ; 0 |
| 16f4: b0 e0 ldi r27, 0x00 ; 0 |
| 16f6: cd 01 movw r24, r26 |
| 16f8: e6 e0 ldi r30, 0x06 ; 6 |
| 16fa: cd b7 in r28, 0x3d ; 61 |
| 16fc: de b7 in r29, 0x3e ; 62 |
| 16fe: 68 c1 rjmp .+720 ; 0x19d0 <__epilogue_restores__+0x18> |
| |
| 00001700 <calloc>: |
| 1700: 0f 93 push r16 |
| 1702: 1f 93 push r17 |
| 1704: cf 93 push r28 |
| 1706: df 93 push r29 |
| 1708: 86 9f mul r24, r22 |
| 170a: 80 01 movw r16, r0 |
| 170c: 87 9f mul r24, r23 |
| 170e: 10 0d add r17, r0 |
| 1710: 96 9f mul r25, r22 |
| 1712: 10 0d add r17, r0 |
| 1714: 11 24 eor r1, r1 |
| 1716: c8 01 movw r24, r16 |
| 1718: 0d d0 rcall .+26 ; 0x1734 <malloc> |
| 171a: ec 01 movw r28, r24 |
| 171c: 00 97 sbiw r24, 0x00 ; 0 |
| 171e: 21 f0 breq .+8 ; 0x1728 <calloc+0x28> |
| 1720: a8 01 movw r20, r16 |
| 1722: 60 e0 ldi r22, 0x00 ; 0 |
| 1724: 70 e0 ldi r23, 0x00 ; 0 |
| 1726: ff d0 rcall .+510 ; 0x1926 <memset> |
| 1728: ce 01 movw r24, r28 |
| 172a: df 91 pop r29 |
| 172c: cf 91 pop r28 |
| 172e: 1f 91 pop r17 |
| 1730: 0f 91 pop r16 |
| 1732: 08 95 ret |
| |
| 00001734 <malloc>: |
| 1734: cf 93 push r28 |
| 1736: df 93 push r29 |
| 1738: ac 01 movw r20, r24 |
| 173a: 02 97 sbiw r24, 0x02 ; 2 |
| 173c: 10 f4 brcc .+4 ; 0x1742 <malloc+0xe> |
| 173e: 42 e0 ldi r20, 0x02 ; 2 |
| 1740: 50 e0 ldi r21, 0x00 ; 0 |
| 1742: a0 91 a6 03 lds r26, 0x03A6 |
| 1746: b0 91 a7 03 lds r27, 0x03A7 |
| 174a: fd 01 movw r30, r26 |
| 174c: c0 e0 ldi r28, 0x00 ; 0 |
| 174e: d0 e0 ldi r29, 0x00 ; 0 |
| 1750: 20 e0 ldi r18, 0x00 ; 0 |
| 1752: 30 e0 ldi r19, 0x00 ; 0 |
| 1754: 20 c0 rjmp .+64 ; 0x1796 <malloc+0x62> |
| 1756: 80 81 ld r24, Z |
| 1758: 91 81 ldd r25, Z+1 ; 0x01 |
| 175a: 84 17 cp r24, r20 |
| 175c: 95 07 cpc r25, r21 |
| 175e: 69 f4 brne .+26 ; 0x177a <malloc+0x46> |
| 1760: 82 81 ldd r24, Z+2 ; 0x02 |
| 1762: 93 81 ldd r25, Z+3 ; 0x03 |
| 1764: 20 97 sbiw r28, 0x00 ; 0 |
| 1766: 19 f0 breq .+6 ; 0x176e <malloc+0x3a> |
| 1768: 9b 83 std Y+3, r25 ; 0x03 |
| 176a: 8a 83 std Y+2, r24 ; 0x02 |
| 176c: 04 c0 rjmp .+8 ; 0x1776 <malloc+0x42> |
| 176e: 90 93 a7 03 sts 0x03A7, r25 |
| 1772: 80 93 a6 03 sts 0x03A6, r24 |
| 1776: cf 01 movw r24, r30 |
| 1778: 32 c0 rjmp .+100 ; 0x17de <malloc+0xaa> |
| 177a: 48 17 cp r20, r24 |
| 177c: 59 07 cpc r21, r25 |
| 177e: 38 f4 brcc .+14 ; 0x178e <malloc+0x5a> |
| 1780: 21 15 cp r18, r1 |
| 1782: 31 05 cpc r19, r1 |
| 1784: 19 f0 breq .+6 ; 0x178c <malloc+0x58> |
| 1786: 82 17 cp r24, r18 |
| 1788: 93 07 cpc r25, r19 |
| 178a: 08 f4 brcc .+2 ; 0x178e <malloc+0x5a> |
| 178c: 9c 01 movw r18, r24 |
| 178e: ef 01 movw r28, r30 |
| 1790: 02 80 ldd r0, Z+2 ; 0x02 |
| 1792: f3 81 ldd r31, Z+3 ; 0x03 |
| 1794: e0 2d mov r30, r0 |
| 1796: 30 97 sbiw r30, 0x00 ; 0 |
| 1798: f1 f6 brne .-68 ; 0x1756 <malloc+0x22> |
| 179a: 21 15 cp r18, r1 |
| 179c: 31 05 cpc r19, r1 |
| 179e: 89 f1 breq .+98 ; 0x1802 <malloc+0xce> |
| 17a0: c9 01 movw r24, r18 |
| 17a2: 84 1b sub r24, r20 |
| 17a4: 95 0b sbc r25, r21 |
| 17a6: 04 97 sbiw r24, 0x04 ; 4 |
| 17a8: 08 f4 brcc .+2 ; 0x17ac <malloc+0x78> |
| 17aa: a9 01 movw r20, r18 |
| 17ac: e0 e0 ldi r30, 0x00 ; 0 |
| 17ae: f0 e0 ldi r31, 0x00 ; 0 |
| 17b0: 26 c0 rjmp .+76 ; 0x17fe <malloc+0xca> |
| 17b2: 8d 91 ld r24, X+ |
| 17b4: 9c 91 ld r25, X |
| 17b6: 11 97 sbiw r26, 0x01 ; 1 |
| 17b8: 82 17 cp r24, r18 |
| 17ba: 93 07 cpc r25, r19 |
| 17bc: e9 f4 brne .+58 ; 0x17f8 <malloc+0xc4> |
| 17be: 48 17 cp r20, r24 |
| 17c0: 59 07 cpc r21, r25 |
| 17c2: 79 f4 brne .+30 ; 0x17e2 <malloc+0xae> |
| 17c4: ed 01 movw r28, r26 |
| 17c6: 8a 81 ldd r24, Y+2 ; 0x02 |
| 17c8: 9b 81 ldd r25, Y+3 ; 0x03 |
| 17ca: 30 97 sbiw r30, 0x00 ; 0 |
| 17cc: 19 f0 breq .+6 ; 0x17d4 <malloc+0xa0> |
| 17ce: 93 83 std Z+3, r25 ; 0x03 |
| 17d0: 82 83 std Z+2, r24 ; 0x02 |
| 17d2: 04 c0 rjmp .+8 ; 0x17dc <malloc+0xa8> |
| 17d4: 90 93 a7 03 sts 0x03A7, r25 |
| 17d8: 80 93 a6 03 sts 0x03A6, r24 |
| 17dc: cd 01 movw r24, r26 |
| 17de: 02 96 adiw r24, 0x02 ; 2 |
| 17e0: 49 c0 rjmp .+146 ; 0x1874 <malloc+0x140> |
| 17e2: 84 1b sub r24, r20 |
| 17e4: 95 0b sbc r25, r21 |
| 17e6: fd 01 movw r30, r26 |
| 17e8: e8 0f add r30, r24 |
| 17ea: f9 1f adc r31, r25 |
| 17ec: 41 93 st Z+, r20 |
| 17ee: 51 93 st Z+, r21 |
| 17f0: 02 97 sbiw r24, 0x02 ; 2 |
| 17f2: 8d 93 st X+, r24 |
| 17f4: 9c 93 st X, r25 |
| 17f6: 3a c0 rjmp .+116 ; 0x186c <malloc+0x138> |
| 17f8: fd 01 movw r30, r26 |
| 17fa: a2 81 ldd r26, Z+2 ; 0x02 |
| 17fc: b3 81 ldd r27, Z+3 ; 0x03 |
| 17fe: 10 97 sbiw r26, 0x00 ; 0 |
| 1800: c1 f6 brne .-80 ; 0x17b2 <malloc+0x7e> |
| 1802: 80 91 a4 03 lds r24, 0x03A4 |
| 1806: 90 91 a5 03 lds r25, 0x03A5 |
| 180a: 89 2b or r24, r25 |
| 180c: 41 f4 brne .+16 ; 0x181e <malloc+0xea> |
| 180e: 80 91 71 00 lds r24, 0x0071 |
| 1812: 90 91 72 00 lds r25, 0x0072 |
| 1816: 90 93 a5 03 sts 0x03A5, r25 |
| 181a: 80 93 a4 03 sts 0x03A4, r24 |
| 181e: 20 91 73 00 lds r18, 0x0073 |
| 1822: 30 91 74 00 lds r19, 0x0074 |
| 1826: 21 15 cp r18, r1 |
| 1828: 31 05 cpc r19, r1 |
| 182a: 41 f4 brne .+16 ; 0x183c <malloc+0x108> |
| 182c: 2d b7 in r18, 0x3d ; 61 |
| 182e: 3e b7 in r19, 0x3e ; 62 |
| 1830: 80 91 6f 00 lds r24, 0x006F |
| 1834: 90 91 70 00 lds r25, 0x0070 |
| 1838: 28 1b sub r18, r24 |
| 183a: 39 0b sbc r19, r25 |
| 183c: e0 91 a4 03 lds r30, 0x03A4 |
| 1840: f0 91 a5 03 lds r31, 0x03A5 |
| 1844: 2e 1b sub r18, r30 |
| 1846: 3f 0b sbc r19, r31 |
| 1848: 24 17 cp r18, r20 |
| 184a: 35 07 cpc r19, r21 |
| 184c: 88 f0 brcs .+34 ; 0x1870 <malloc+0x13c> |
| 184e: ca 01 movw r24, r20 |
| 1850: 02 96 adiw r24, 0x02 ; 2 |
| 1852: 28 17 cp r18, r24 |
| 1854: 39 07 cpc r19, r25 |
| 1856: 60 f0 brcs .+24 ; 0x1870 <malloc+0x13c> |
| 1858: cf 01 movw r24, r30 |
| 185a: 84 0f add r24, r20 |
| 185c: 95 1f adc r25, r21 |
| 185e: 02 96 adiw r24, 0x02 ; 2 |
| 1860: 90 93 a5 03 sts 0x03A5, r25 |
| 1864: 80 93 a4 03 sts 0x03A4, r24 |
| 1868: 41 93 st Z+, r20 |
| 186a: 51 93 st Z+, r21 |
| 186c: cf 01 movw r24, r30 |
| 186e: 02 c0 rjmp .+4 ; 0x1874 <malloc+0x140> |
| 1870: 80 e0 ldi r24, 0x00 ; 0 |
| 1872: 90 e0 ldi r25, 0x00 ; 0 |
| 1874: df 91 pop r29 |
| 1876: cf 91 pop r28 |
| 1878: 08 95 ret |
| |
| 0000187a <free>: |
| 187a: cf 93 push r28 |
| 187c: df 93 push r29 |
| 187e: 00 97 sbiw r24, 0x00 ; 0 |
| 1880: 09 f4 brne .+2 ; 0x1884 <free+0xa> |
| 1882: 4e c0 rjmp .+156 ; 0x1920 <free+0xa6> |
| 1884: ec 01 movw r28, r24 |
| 1886: 22 97 sbiw r28, 0x02 ; 2 |
| 1888: 1b 82 std Y+3, r1 ; 0x03 |
| 188a: 1a 82 std Y+2, r1 ; 0x02 |
| 188c: a0 91 a6 03 lds r26, 0x03A6 |
| 1890: b0 91 a7 03 lds r27, 0x03A7 |
| 1894: 10 97 sbiw r26, 0x00 ; 0 |
| 1896: 11 f1 breq .+68 ; 0x18dc <free+0x62> |
| 1898: 40 e0 ldi r20, 0x00 ; 0 |
| 189a: 50 e0 ldi r21, 0x00 ; 0 |
| 189c: 01 c0 rjmp .+2 ; 0x18a0 <free+0x26> |
| 189e: dc 01 movw r26, r24 |
| 18a0: ac 17 cp r26, r28 |
| 18a2: bd 07 cpc r27, r29 |
| 18a4: 00 f1 brcs .+64 ; 0x18e6 <free+0x6c> |
| 18a6: bb 83 std Y+3, r27 ; 0x03 |
| 18a8: aa 83 std Y+2, r26 ; 0x02 |
| 18aa: fe 01 movw r30, r28 |
| 18ac: 21 91 ld r18, Z+ |
| 18ae: 31 91 ld r19, Z+ |
| 18b0: e2 0f add r30, r18 |
| 18b2: f3 1f adc r31, r19 |
| 18b4: ea 17 cp r30, r26 |
| 18b6: fb 07 cpc r31, r27 |
| 18b8: 71 f4 brne .+28 ; 0x18d6 <free+0x5c> |
| 18ba: 2e 5f subi r18, 0xFE ; 254 |
| 18bc: 3f 4f sbci r19, 0xFF ; 255 |
| 18be: 8d 91 ld r24, X+ |
| 18c0: 9c 91 ld r25, X |
| 18c2: 11 97 sbiw r26, 0x01 ; 1 |
| 18c4: 82 0f add r24, r18 |
| 18c6: 93 1f adc r25, r19 |
| 18c8: 99 83 std Y+1, r25 ; 0x01 |
| 18ca: 88 83 st Y, r24 |
| 18cc: fd 01 movw r30, r26 |
| 18ce: 82 81 ldd r24, Z+2 ; 0x02 |
| 18d0: 93 81 ldd r25, Z+3 ; 0x03 |
| 18d2: 9b 83 std Y+3, r25 ; 0x03 |
| 18d4: 8a 83 std Y+2, r24 ; 0x02 |
| 18d6: 41 15 cp r20, r1 |
| 18d8: 51 05 cpc r21, r1 |
| 18da: 59 f4 brne .+22 ; 0x18f2 <free+0x78> |
| 18dc: d0 93 a7 03 sts 0x03A7, r29 |
| 18e0: c0 93 a6 03 sts 0x03A6, r28 |
| 18e4: 1d c0 rjmp .+58 ; 0x1920 <free+0xa6> |
| 18e6: fd 01 movw r30, r26 |
| 18e8: 82 81 ldd r24, Z+2 ; 0x02 |
| 18ea: 93 81 ldd r25, Z+3 ; 0x03 |
| 18ec: ad 01 movw r20, r26 |
| 18ee: 00 97 sbiw r24, 0x00 ; 0 |
| 18f0: b1 f6 brne .-84 ; 0x189e <free+0x24> |
| 18f2: fa 01 movw r30, r20 |
| 18f4: d3 83 std Z+3, r29 ; 0x03 |
| 18f6: c2 83 std Z+2, r28 ; 0x02 |
| 18f8: 21 91 ld r18, Z+ |
| 18fa: 31 91 ld r19, Z+ |
| 18fc: e2 0f add r30, r18 |
| 18fe: f3 1f adc r31, r19 |
| 1900: ec 17 cp r30, r28 |
| 1902: fd 07 cpc r31, r29 |
| 1904: 69 f4 brne .+26 ; 0x1920 <free+0xa6> |
| 1906: 2e 5f subi r18, 0xFE ; 254 |
| 1908: 3f 4f sbci r19, 0xFF ; 255 |
| 190a: 88 81 ld r24, Y |
| 190c: 99 81 ldd r25, Y+1 ; 0x01 |
| 190e: 82 0f add r24, r18 |
| 1910: 93 1f adc r25, r19 |
| 1912: fa 01 movw r30, r20 |
| 1914: 91 83 std Z+1, r25 ; 0x01 |
| 1916: 80 83 st Z, r24 |
| 1918: 8a 81 ldd r24, Y+2 ; 0x02 |
| 191a: 9b 81 ldd r25, Y+3 ; 0x03 |
| 191c: 93 83 std Z+3, r25 ; 0x03 |
| 191e: 82 83 std Z+2, r24 ; 0x02 |
| 1920: df 91 pop r29 |
| 1922: cf 91 pop r28 |
| 1924: 08 95 ret |
| |
| 00001926 <memset>: |
| 1926: dc 01 movw r26, r24 |
| 1928: 01 c0 rjmp .+2 ; 0x192c <memset+0x6> |
| 192a: 6d 93 st X+, r22 |
| 192c: 41 50 subi r20, 0x01 ; 1 |
| 192e: 50 40 sbci r21, 0x00 ; 0 |
| 1930: e0 f7 brcc .-8 ; 0x192a <memset+0x4> |
| 1932: 08 95 ret |
| |
| 00001934 <__udivmodqi4>: |
| 1934: 99 1b sub r25, r25 |
| 1936: 79 e0 ldi r23, 0x09 ; 9 |
| 1938: 04 c0 rjmp .+8 ; 0x1942 <__udivmodqi4_ep> |
| |
| 0000193a <__udivmodqi4_loop>: |
| 193a: 99 1f adc r25, r25 |
| 193c: 96 17 cp r25, r22 |
| 193e: 08 f0 brcs .+2 ; 0x1942 <__udivmodqi4_ep> |
| 1940: 96 1b sub r25, r22 |
| |
| 00001942 <__udivmodqi4_ep>: |
| 1942: 88 1f adc r24, r24 |
| 1944: 7a 95 dec r23 |
| 1946: c9 f7 brne .-14 ; 0x193a <__udivmodqi4_loop> |
| 1948: 80 95 com r24 |
| 194a: 08 95 ret |
| |
| 0000194c <__udivmodhi4>: |
| 194c: aa 1b sub r26, r26 |
| 194e: bb 1b sub r27, r27 |
| 1950: 51 e1 ldi r21, 0x11 ; 17 |
| 1952: 07 c0 rjmp .+14 ; 0x1962 <__udivmodhi4_ep> |
| |
| 00001954 <__udivmodhi4_loop>: |
| 1954: aa 1f adc r26, r26 |
| 1956: bb 1f adc r27, r27 |
| 1958: a6 17 cp r26, r22 |
| 195a: b7 07 cpc r27, r23 |
| 195c: 10 f0 brcs .+4 ; 0x1962 <__udivmodhi4_ep> |
| 195e: a6 1b sub r26, r22 |
| 1960: b7 0b sbc r27, r23 |
| |
| 00001962 <__udivmodhi4_ep>: |
| 1962: 88 1f adc r24, r24 |
| 1964: 99 1f adc r25, r25 |
| 1966: 5a 95 dec r21 |
| 1968: a9 f7 brne .-22 ; 0x1954 <__udivmodhi4_loop> |
| 196a: 80 95 com r24 |
| 196c: 90 95 com r25 |
| 196e: bc 01 movw r22, r24 |
| 1970: cd 01 movw r24, r26 |
| 1972: 08 95 ret |
| |
| 00001974 <__udivmodsi4>: |
| 1974: a1 e2 ldi r26, 0x21 ; 33 |
| 1976: 1a 2e mov r1, r26 |
| 1978: aa 1b sub r26, r26 |
| 197a: bb 1b sub r27, r27 |
| 197c: fd 01 movw r30, r26 |
| 197e: 0d c0 rjmp .+26 ; 0x199a <__udivmodsi4_ep> |
| |
| 00001980 <__udivmodsi4_loop>: |
| 1980: aa 1f adc r26, r26 |
| 1982: bb 1f adc r27, r27 |
| 1984: ee 1f adc r30, r30 |
| 1986: ff 1f adc r31, r31 |
| 1988: a2 17 cp r26, r18 |
| 198a: b3 07 cpc r27, r19 |
| 198c: e4 07 cpc r30, r20 |
| 198e: f5 07 cpc r31, r21 |
| 1990: 20 f0 brcs .+8 ; 0x199a <__udivmodsi4_ep> |
| 1992: a2 1b sub r26, r18 |
| 1994: b3 0b sbc r27, r19 |
| 1996: e4 0b sbc r30, r20 |
| 1998: f5 0b sbc r31, r21 |
| |
| 0000199a <__udivmodsi4_ep>: |
| 199a: 66 1f adc r22, r22 |
| 199c: 77 1f adc r23, r23 |
| 199e: 88 1f adc r24, r24 |
| 19a0: 99 1f adc r25, r25 |
| 19a2: 1a 94 dec r1 |
| 19a4: 69 f7 brne .-38 ; 0x1980 <__udivmodsi4_loop> |
| 19a6: 60 95 com r22 |
| 19a8: 70 95 com r23 |
| 19aa: 80 95 com r24 |
| 19ac: 90 95 com r25 |
| 19ae: 9b 01 movw r18, r22 |
| 19b0: ac 01 movw r20, r24 |
| 19b2: bd 01 movw r22, r26 |
| 19b4: cf 01 movw r24, r30 |
| 19b6: 08 95 ret |
| |
| 000019b8 <__epilogue_restores__>: |
| 19b8: 2a 88 ldd r2, Y+18 ; 0x12 |
| 19ba: 39 88 ldd r3, Y+17 ; 0x11 |
| 19bc: 48 88 ldd r4, Y+16 ; 0x10 |
| 19be: 5f 84 ldd r5, Y+15 ; 0x0f |
| 19c0: 6e 84 ldd r6, Y+14 ; 0x0e |
| 19c2: 7d 84 ldd r7, Y+13 ; 0x0d |
| 19c4: 8c 84 ldd r8, Y+12 ; 0x0c |
| 19c6: 9b 84 ldd r9, Y+11 ; 0x0b |
| 19c8: aa 84 ldd r10, Y+10 ; 0x0a |
| 19ca: b9 84 ldd r11, Y+9 ; 0x09 |
| 19cc: c8 84 ldd r12, Y+8 ; 0x08 |
| 19ce: df 80 ldd r13, Y+7 ; 0x07 |
| 19d0: ee 80 ldd r14, Y+6 ; 0x06 |
| 19d2: fd 80 ldd r15, Y+5 ; 0x05 |
| 19d4: 0c 81 ldd r16, Y+4 ; 0x04 |
| 19d6: 1b 81 ldd r17, Y+3 ; 0x03 |
| 19d8: aa 81 ldd r26, Y+2 ; 0x02 |
| 19da: b9 81 ldd r27, Y+1 ; 0x01 |
| 19dc: ce 0f add r28, r30 |
| 19de: d1 1d adc r29, r1 |
| 19e0: 0f b6 in r0, 0x3f ; 63 |
| 19e2: f8 94 cli |
| 19e4: de bf out 0x3e, r29 ; 62 |
| 19e6: 0f be out 0x3f, r0 ; 63 |
| 19e8: cd bf out 0x3d, r28 ; 61 |
| 19ea: ed 01 movw r28, r26 |
| 19ec: 08 95 ret |