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Ignore whitespace Rev 243 → Rev 244

/trunk/fifo.c
1,10 → 1,12
#include "fifo.h"
 
u8 fifo_init (fifo_t *f, u8 *buffer, const u16 size)
u8 fifo_init (fifo_t* f, u8* buffer, const u16 size, u16 putvicsource, u16 getvicsource)
{
if(f == NULL) return(0);
f->buffer = buffer;
f->size = size;
f->putvicsource = putvicsource;
f->getvicsource = getvicsource;
fifo_purge(f);
return(1);
}
12,26 → 14,22
u8 fifo_put (fifo_t *f, const u8 data)
{
if (f->count >= f->size) return(0); // return 0 in case of FIFO overflow.
 
u8 * pwrite = f->pwrite;
 
*(pwrite++) = data; // copy data byte to buffer
if(pwrite >= f->buffer + f->size) pwrite = f->buffer; // start at the begining after reaching the end
f->pwrite = pwrite;
if(f->putvicsource != NO_ITLine) VIC_ITCmd(f->putvicsource, DISABLE);
*(f->pwrite++) = data; // copy data byte to buffer
if(f->pwrite >= f->buffer + f->size) f->pwrite = f->buffer; // start at the begining after reaching the end
f->count++;
return 1;
if(f->putvicsource != NO_ITLine) VIC_ITCmd(f->putvicsource, ENABLE);
return(1);
}
 
u8 fifo_get (fifo_t *f, u8 *pdata)
{
if((f == NULL) || (pdata == NULL)) return(0);
if(!f->count) return(0);
 
u8 *pread = f->pread;
*pdata = *(pread++);
if(pread >= f->buffer + f->size) pread = f->buffer; // start at the begining after reaching the end
f->pread = pread;
if(f->getvicsource != NO_ITLine) VIC_ITCmd(f->getvicsource, DISABLE);
*pdata = *(f->pread++);
if(f->pread >= f->buffer + f->size) f->pread = f->buffer; // start at the begining after reaching the end
f->count--;
if(f->getvicsource != NO_ITLine) VIC_ITCmd(f->getvicsource, ENABLE);
return(1);
}
 
/trunk/fifo.h
3,15 → 3,18
 
#include <stdio.h>
#include "91x_lib.h"
#define NO_ITLine 0xFFFF
 
// the fifo object
typedef struct
{
u8 *buffer; // pointer to start of the ringbuffer
u8 count; // number of characters in FIFO
u16 size; // buffer size
u8 *pread; // read pointer
u8 *pwrite; // write pointer
u8 *buffer; // pointer to start of the ringbuffer
u16 count; // number of bytes in FIFO
u16 size; // buffer size
u8 *pread; // read pointer
u8 *pwrite; // write pointer
u16 putvicsource; // IRQ source to block, during put
u16 getvicsource; // IRQ source to block, during get
} fifo_t;
 
/*
19,7 → 22,7
The FIFO uses the buffer 'buf' which byte length must 'size'.
Returns 1 on success ans 0 in case of an error.
*/
u8 fifo_init (fifo_t* f, u8* buf, const u16 size);
u8 fifo_init (fifo_t* f, u8* buffer, const u16 size, u16 putvicsource, u16 getvicsource);
 
/*
Puts a byte into the FIFO. Returns 1 on success and 0 in case of FIFO overflow.
/trunk/main.c
347,7 → 347,7
// initialize adc
Analog_Init();
// initialize usb
//USB_ConfigInit();
USB_ConfigInit();
// initialize SPI0 to FC
SPI0_Init();
// initialize i2c bus (needs Timer 1)
388,6 → 388,7
VIC_Config(EXTIT3_ITLine, VIC_IRQ, PRIORITY_SW);
// enable interrupts
VIC_ITCmd(EXTIT3_ITLine, ENABLE);
 
for (;;) // the endless main loop
{
UART0_ProcessRxData(); // process request
397,7 → 398,6
UART1_TransmitTxData(); // send answer
UART2_TransmitTxData(); // send answer
USB_TransmitTxData(); // send answer
 
SPI0_UpdateBuffer(); // handle new SPI Data
// ---------------- Error Check Timing ----------------------------
if(CheckDelay(TimerCheckError))
/trunk/mkprotocol.c
203,7 → 203,8
{
pRxBuff->pData[pRxBuff->Position++] = c; // copy byte to rxd buffer
pRxBuff->DataBytes++;
if (c == '\r') // termination character received
// termination character received and sync has been established
if ((c == '\r') && (pRxBuff->pData[0]== '#'))
{
// calculate checksum from transmitted data
u16 crc = 0, i;
217,7 → 218,8
crc2 = '=' + crc % 64;
// compare checksum to transmitted checksum bytes
if((crc1 == pRxBuff->pData[pRxBuff->Position-3]) && (crc2 == pRxBuff->pData[pRxBuff->Position-2]))
{ // checksum is valid
{
// checksum is valid
pRxBuff->Position = 0;
pRxBuff->Locked = TRUE; // lock the rxd buffer
// if 2nd byte is an 'R' start bootloader
/trunk/spi_slave.c
251,7 → 251,7
SSP_Init(SSP0, &SSP_InitStructure);
SSP_ITConfig(SSP0, SSP_IT_RxFifo | SSP_IT_RxTimeOut, ENABLE);
 
fifo_init(&CompassCalcStateFiFo, CompassCalStateQueue, sizeof(CompassCalStateQueue));
fifo_init(&CompassCalcStateFiFo, CompassCalStateQueue, sizeof(CompassCalStateQueue), NO_ITLine, NO_ITLine);
 
SSP_Cmd(SSP0, ENABLE);
// initialize the syncbytes in the tx buffer
/trunk/uart1.c
108,12 → 108,12
fifo_t UART1_rx_fifo;
 
// the rx buffer
#define UART1_RX_BUFFER_LEN 150
#define UART1_RX_BUFFER_LEN 200
u8 UART1_rbuffer[UART1_RX_BUFFER_LEN];
Buffer_t UART1_rx_buffer;
 
// the tx buffer
#define UART1_TX_BUFFER_LEN 150
#define UART1_TX_BUFFER_LEN 200
u8 UART1_tbuffer[UART1_TX_BUFFER_LEN];
Buffer_t UART1_tx_buffer;
 
190,8 → 190,8
// initialize rxd buffer
Buffer_Init(&UART1_rx_buffer, UART1_rbuffer, UART1_RX_BUFFER_LEN);
 
// initialize the rx fifo
fifo_init(&UART1_rx_fifo, UART1_rxfifobuffer, UART1_RX_FIFO_LEN);
// initialize the rx fifo, block UART IRQ geting a byte from fifo
fifo_init(&UART1_rx_fifo, UART1_rxfifobuffer, UART1_RX_FIFO_LEN, NO_ITLine, UART1_ITLine);
 
SCU_APBPeriphClockConfig(__UART1, ENABLE); // Enable the UART1 Clock
SCU_APBPeriphClockConfig(__GPIO3, ENABLE); // Enable the GPIO3 Clock
240,7 → 240,7
UART_Cmd(UART1, ENABLE); // enable uart 1
// configure the uart 1 interupt line
VIC_Config(UART1_ITLine, VIC_IRQ, PRIORITY_UART1);
// enable the uart 1 IRQ
// enable the uart 1 IRQ
VIC_ITCmd(UART1_ITLine, ENABLE);
 
// initialize the debug timer
354,9 → 354,11
u8 c;
// if rx buffer is not locked
if(UART1_rx_buffer.Locked == FALSE)
{ //collect data from primary rx fifo
{
//collect data from primary rx fifo
while(fifo_get(&UART1_rx_fifo, &c))
{ // break if complete frame is collected
{
// break if complete frame is collected
if(MKProtocol_CollectSerialFrame(&UART1_rx_buffer, c)) break;
}
}
679,9 → 681,6
}
else if( (( (UART1_DebugData_Interval > 0) && CheckDelay(UART1_DebugData_Timer)) || UART1_Request_DebugData) && (UART1_tx_buffer.Locked == FALSE))
{
DebugOut.Analog[24] = MagVector.X;
DebugOut.Analog[25] = MagVector.Y;
DebugOut.Analog[26] = MagVector.Z;
MKProtocol_CreateSerialFrame(&UART1_tx_buffer, 'D', NC_ADDRESS, 1,(u8 *)&DebugOut, sizeof(DebugOut));
UART1_DebugData_Timer = SetDelay(UART1_DebugData_Interval);
UART1_Request_DebugData = FALSE;
/trunk/ubx.c
171,7 → 171,7
volatile ubx_nav_velned_t UbxVelNed = {0,0,0,0,0,0,0,0,0, INVALID};
 
// shared buffer
gps_data_t GPSData = {{0,0,0,INVALID},0,0,0,0,0,0,0, INVALID};
gps_data_t GPSData = {200,{0,0,0,INVALID},0,0,0,0,0,0,0, INVALID};
DateTime_t GPSDateTime = {0,0,0,0,0,0,0, INVALID};
 
#define UBX_TIMEOUT 500 // 500 ms
280,6 → 280,8
{
static u32 Msg_Count_Timeout = 0;
static u8 Msg_Count = 0;
static u32 LastTimeStamp = 0;
u32 TimeStamp;
 
// the timeout is used to detect the delay between two message sets
// and is used for synchronisation so that always a set is collected
299,10 → 301,16
{
UBX_Timeout = SetDelay(UBX_TIMEOUT);
DebugOut.Analog[9]++;
 
// update GPS data only if the status is INVALID or PROCESSED and the last ubx message was received within less than 100 ms
if(GPSData.Status != NEWDATA) // if last data were processed
{ // wait for new data at all neccesary ubx messages
GPSData.Status = INVALID;
// update message cycle time
TimeStamp = CountMilliseconds;
GPSData.MsgCycleTime = (u16)(TimeStamp - LastTimeStamp);
LastTimeStamp = TimeStamp;
DebugOut.Analog[16] = GPSData.MsgCycleTime;
// NAV SOL
GPSData.Flags = UbxSol.Flags;
GPSData.NumOfSats = UbxSol.numSV;
/trunk/ubx.h
29,6 → 29,7
 
typedef struct
{
u16 MsgCycleTime; // time in ms since last gps data
GPS_Pos_t Position; // Lat/Lon/Alt
u8 Flags; // Status Flags
u8 NumOfSats; // number of satelites