Rev 426 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 426 | killagreg | 1 | #include <avr/io.h> |
| 2 | #include <avr/interrupt.h> |
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| 3 | |||
| 4 | #include "main.h" |
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| 5 | #include "uart1.h" |
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| 434 | killagreg | 6 | #include "printf_P.h" |
| 426 | killagreg | 7 | #include "ubx.h" |
| 8 | |||
| 9 | |||
| 10 | /****************************************************************/ |
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| 11 | /* Initialization of the USART1 */ |
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| 12 | /****************************************************************/ |
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| 13 | void USART1_Init (void) |
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| 14 | { |
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| 434 | killagreg | 15 | printf("\r\n UART1 init..."); |
| 426 | killagreg | 16 | // USART1 Control and Status Register A, B, C and baud rate register |
| 17 | uint8_t sreg = SREG; |
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| 18 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
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| 19 | |||
| 20 | // disable all interrupts before reconfiguration |
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| 21 | cli(); |
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| 22 | |||
| 23 | // disable RX-Interrupt |
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| 24 | UCSR1B &= ~(1 << RXCIE1); |
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| 25 | // disable TX-Interrupt |
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| 26 | UCSR1B &= ~(1 << TXCIE1); |
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| 27 | // disable DRE-Interrupt |
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| 28 | UCSR1B &= ~(1 << UDRIE1); |
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| 29 | |||
| 30 | // set direction of RXD1 and TXD1 pins |
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| 31 | // set RXD1 (PD2) as an input pin |
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| 32 | PORTD |= (1 << PORTD2); |
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| 33 | DDRD &= ~(1 << DDD2); |
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| 34 | |||
| 35 | // set TXD1 (PD3) as an output pin |
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| 36 | PORTD |= (1 << PORTD3); |
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| 37 | DDRD |= (1 << DDD3); |
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| 38 | |||
| 39 | // USART0 Baud Rate Register |
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| 40 | // set clock divider |
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| 41 | UBRR1H = (uint8_t)(ubrr>>8); |
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| 42 | UBRR1L = (uint8_t)ubrr; |
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| 43 | |||
| 44 | // enable double speed operation |
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| 45 | UCSR1A |= (1 << U2X1); |
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| 46 | // enable receiver and transmitter |
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| 47 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
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| 48 | // set asynchronous mode |
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| 49 | UCSR1C &= ~(1 << UMSEL11); |
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| 50 | UCSR1C &= ~(1 << UMSEL10); |
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| 51 | // no parity |
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| 52 | UCSR1C &= ~(1 << UPM11); |
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| 53 | UCSR1C &= ~(1 << UPM10); |
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| 54 | // 1 stop bit |
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| 55 | UCSR1C &= ~(1 << USBS1); |
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| 56 | // 8-bit |
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| 57 | UCSR1B &= ~(1 << UCSZ12); |
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| 58 | UCSR1C |= (1 << UCSZ11); |
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| 59 | UCSR1C |= (1 << UCSZ10); |
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| 60 | |||
| 61 | // flush receive buffer explicit |
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| 62 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
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| 63 | |||
| 64 | // enable interrupts at the end |
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| 65 | // enable RX-Interrupt |
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| 66 | UCSR1B |= (1 << RXCIE1); |
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| 67 | // enable TX-Interrupt |
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| 68 | UCSR1B |= (1 << TXCIE1); |
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| 69 | // enable DRE interrupt |
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| 70 | //UCSR1B |= (1 << UDRIE1); |
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| 71 | |||
| 72 | |||
| 73 | // restore global interrupt flags |
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| 74 | SREG = sreg; |
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| 434 | killagreg | 75 | sei(); |
| 76 | printf("ok"); |
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| 426 | killagreg | 77 | } |
| 78 | |||
| 79 | /****************************************************************/ |
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| 80 | /* USART1 transmitter ISR */ |
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| 81 | /****************************************************************/ |
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| 82 | /*ISR(USART1_TX_vect) |
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| 83 | { |
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| 84 | |||
| 85 | } |
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| 86 | */ |
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| 87 | /****************************************************************/ |
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| 88 | /* USART1 receiver ISR */ |
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| 89 | /****************************************************************/ |
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| 90 | ISR(USART1_RX_vect) |
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| 91 | { |
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| 92 | uint8_t c; |
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| 93 | c = UDR1; // get data byte |
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| 94 | |||
| 95 | UBX_Parser(c); // and put it into the ubx protocol parser |
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| 96 | |||
| 97 | } |