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Rev	Author	Line No.	Line
196	killagreg	1	/****************** (C) COPYRIGHT 2008 STMicroelectronics ******************
1	ingob	2	* File Name : 91x_map.h
		3	* Author : MCD Application Team
196	killagreg	4	* Version : V2.1
		5	* Date : 12/22/2008
1	ingob	6	* Description : Peripherals registers definition and memory mapping.
		7	********************************************************************************
		8	* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
		9	* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
		10	* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
		11	* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
		12	* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
		13	* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
		14	*******************************************************************************/
		15
		16	/* Define to prevent recursive inclusion ------------------------------------ */
		17	#ifndef __91x_MAP_H
		18	#define __91x_MAP_H
		19
		20	#ifndef EXT
		21	#define EXT extern
		22	#endif /* EXT */
		23
		24	/* Includes ------------------------------------------------------------------*/
		25	#include "91x_conf.h"
		26	#include "91x_type.h"
		27
		28	/******************************************************************************/
		29	/* IP registers structures */
		30	/******************************************************************************/
		31
		32	/------------------------------------ FMI -----------------------------------/
		33
		34	typedef struct
		35	{
		36	vu32 BBSR; /* Boot Bank Size Register */
		37	vu32 NBBSR; /* Non-Boot Bank Size Register */
		38	vu32 EMPTY1;
		39	vu32 BBADR; /* Boot Bank Base Address Register */
		40	vu32 NBBADR; /* Non-Boot Bank Base Address Register */
		41	vu32 EMPTY2;
		42	vu32 CR; /* Control Register */
		43	vu32 SR; /* Status Register */
		44	vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
		45	} FMI_TypeDef;
		46
		47	/---------------------- Analog to Digital Convertor ------------------------/
		48
		49	typedef struct
		50	{
		51	vu16 CR; /* Control Register */
		52	vu16 EMPTY1;
		53	vu16 CCR; /* Channel Configuration Register */
		54	vu16 EMPTY2;
		55	vu16 HTR; /* Higher Threshold Register */
		56	vu16 EMPTY3;
		57	vu16 LTR; /* Lower Threshold Register */
		58	vu16 EMPTY4;
		59	vu16 CRR; /* Compare Result Register */
		60	vu16 EMPTY5;
		61	vu16 DR0; /* Data Register for Channel 0 */
		62	vu16 EMPTY6;
		63	vu16 DR1; /* Data Register for Channel 1 */
		64	vu16 EMPTY7;
		65	vu16 DR2; /* Data Register for Channel 2 */
		66	vu16 EMPTY8;
		67	vu16 DR3; /* Data Register for Channel 3 */
		68	vu16 EMPTY9;
		69	vu16 DR4; /* Data Register for Channel 4 */
		70	vu16 EMPTY10;
		71	vu16 DR5; /* Data Register for Channel 5 */
		72	vu16 EMPTY11;
		73	vu16 DR6; /* Data Register for Channel 6 */
		74	vu16 EMPTY12;
		75	vu16 DR7; /* Data Register for Channel 7 */
		76	vu16 EMPTY13;
		77	vu16 PRS; /* Prescaler Value Register */
		78	vu16 EMPTY14;
196	killagreg	79	vu16 DDR; /* ADC DMA Data Register */
		80	vu16 EMPTY15;
		81	vu16 CR2; /* ADC Control Register2 */
		82	vu16 EMPTY16;
1	ingob	83	} ADC_TypeDef;
		84
		85	/--------------------- AHB APB BRIDGE registers strcture --------------------/
		86
		87	typedef struct
		88	{
		89	vu32 BSR; /* Bridge Status Register */
		90	vu32 BCR; /* Bridge Configuration Register */
		91	vu32 PAER; /* Peripheral Address Error register */
		92	} AHBAPB_TypeDef;
		93
		94	/--------------- Controller Area Network Interface Register -----------------/
		95
		96	typedef struct
		97	{
		98	vu16 CRR; /* IFn Command request Register */
		99	vu16 EMPTY1;
		100	vu16 CMR; /* IFn Command Mask Register */
		101	vu16 EMPTY2;
		102	vu16 M1R; /* IFn Message Mask 1 Register */
		103	vu16 EMPTY3;
		104	vu16 M2R; /* IFn Message Mask 2 Register */
		105	vu16 EMPTY4;
		106	vu16 A1R; /* IFn Message Arbitration 1 Register */
		107	vu16 EMPTY5;
		108	vu16 A2R; /* IFn Message Arbitration 2 Register */
		109	vu16 EMPTY6;
		110	vu16 MCR; /* IFn Message Control Register */
		111	vu16 EMPTY7;
		112	vu16 DA1R; /* IFn DATA A 1 Register */
		113	vu16 EMPTY8;
		114	vu16 DA2R; /* IFn DATA A 2 Register */
		115	vu16 EMPTY9;
		116	vu16 DB1R; /* IFn DATA B 1 Register */
		117	vu16 EMPTY10;
		118	vu16 DB2R; /* IFn DATA B 2 Register */
		119	vu16 EMPTY11[27];
		120	} CAN_MsgObj_TypeDef;
		121
		122	typedef struct
		123	{
		124	vu16 CR; /* Control Register */
		125	vu16 EMPTY1;
		126	vu16 SR; /* Status Register */
		127	vu16 EMPTY2;
		128	vu16 ERR; /* Error counter Register */
		129	vu16 EMPTY3;
		130	vu16 BTR; /* Bit Timing Register */
		131	vu16 EMPTY4;
		132	vu16 IDR; /* Interrupt Identifier Register */
		133	vu16 EMPTY5;
		134	vu16 TESTR; /* Test Register */
		135	vu16 EMPTY6;
		136	vu16 BRPR; /* BRP Extension Register */
		137	vu16 EMPTY7[3];
		138	CAN_MsgObj_TypeDef sMsgObj[2];
		139	vu16 EMPTY8[16];
		140	vu16 TXR1R; /* Transmission request 1 Register */
		141	vu16 EMPTY9;
		142	vu16 TXR2R; /* Transmission Request 2 Register */
		143	vu16 EMPTY10[13];
		144	vu16 ND1R; /* New Data 1 Register */
		145	vu16 EMPTY11;
		146	vu16 ND2R; /* New Data 2 Register */
		147	vu16 EMPTY12[13];
		148	vu16 IP1R; /* Interrupt Pending 1 Register */
		149	vu16 EMPTY13;
		150	vu16 IP2R; /* Interrupt Pending 2 Register */
		151	vu16 EMPTY14[13];
		152	vu16 MV1R; /* Message Valid 1 Register */
		153	vu16 EMPTY15;
		154	vu16 MV2R; /* Message VAlid 2 Register */
		155	vu16 EMPTY16;
		156	} CAN_TypeDef;
		157
		158	/----------------------- System Control Unit---------------------------------/
		159
		160	typedef struct
		161	{
		162	vu32 CLKCNTR; /* Clock Control Register */
		163	vu32 PLLCONF; /* PLL Configuration Register */
		164	vu32 SYSSTATUS; /* System Status Register */
		165	vu32 PWRMNG; /* Power Management Register */
		166	vu32 ITCMSK; /* Interrupt Mask Register */
196	killagreg	167	vu32 PCGR0; /* Peripheral Clock Gating Register 0 */
1	ingob	168	vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
		169	vu32 PRR0; /* Peripheral Reset Register 0 */
		170	vu32 PRR1; /* Peripheral Reset Register 1 */
		171	vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
		172	vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
		173	vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
		174	vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
		175	vu32 SCR0; /* System Configuration Register 0 */
		176	vu32 SCR1; /* System Configuration Register 1 */
		177	vu32 SCR2; /* System Configuration Register 2 */
		178	u32 EMPTY1;
		179	vu32 GPIOOUT[8]; /* GPIO Output Registers */
		180	vu32 GPIOIN[8]; /* GPIO Input Registers */
		181	vu32 GPIOTYPE[10]; /* GPIO Type Registers */
		182	vu32 GPIOEMI; /* GPIO EMI Selector Register */
		183	vu32 WKUPSEL; /* Wake-Up Selection Register */
		184	u32 EMPTY2[2];
		185	vu32 GPIOANA; /* GPIO Analag mode Register */
		186	} SCU_TypeDef;
		187
		188	/------------------------- DMA Channelx Registers ---------------------------/
		189
		190	typedef struct
		191	{
		192	vu32 SRC; /* Channelx Source Address Register */
		193	vu32 DES; /* Channelx Destination Address Register */
		194	vu32 LLI; /* Channelx Lincked List Item Register */
		195	vu32 CC; /* Channelx Contol Register */
		196	vu32 CCNF; /* Channelx Configuration Register */
		197	} DMA_Channel_TypeDef;
		198
		199	/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
		200
		201	/----------------------------- DMA Controller -------------------------------/
		202
		203	typedef struct
		204	{
		205	vu32 ISR; /* Interrupt Status Register */
		206	vu32 TCISR; /* Terminal Count Interrupt Status Register */
		207	vu32 TCICR; /* Terminal CountInterrupt Clear Register */
		208	vu32 EISR; /* Error Interrupt Status Register */
		209	vu32 EICR; /* Error Interrupt Clear Register */
		210	vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
		211	vu32 ERISR; /* Raw Error Interrupt Status Register */
		212	vu32 ENCSR; /* Enabled Channel Status Register */
		213	vu32 SBRR; /* Software Burst Request Register */
		214	vu32 SSRR; /* Software Single Request Register */
		215	vu32 SLBRR; /* Software Last Burst Request Register */
		216	vu32 SLSRR; /* Software Last Single Request Register */
		217	vu32 CNFR; /* Configuration Register */
		218	vu32 SYNR; /* Syncronization Register */
		219	} DMA_TypeDef;
		220
		221	/--------------------------------- TIM Timer --------------------------------/
		222
		223	typedef struct
		224	{
		225	vu16 IC1R; /* Input Capture 1 Register */
		226	vu16 EMPTY1;
		227	vu16 IC2R; /* Input Capture 2 Register */
		228	vu16 EMPTY2;
		229	vu16 OC1R; /* Output Compare 1 Register */
		230	vu16 EMPTY3;
		231	vu16 OC2R; /* Output Compare 2 Register */
		232	vu16 EMPTY4;
		233	vu16 CNTR; /* Counter Register */
		234	vu16 EMPTY5;
		235	vu16 CR1; /* Control Register 1 */
		236	vu16 EMPTY6;
		237	vu16 CR2; /* Control Register 2 */
		238	vu16 EMPTY7;
		239	vu16 SR; /* Status Register */
		240	vu16 EMPTY8;
		241	} TIM_TypeDef;
		242
		243	/---------------------------- EMI Bankx Registers ---------------------------/
		244
		245	typedef struct
		246	{
		247	vu32 ICR; /* Bankx Idle Cycle Control Register */
		248	vu32 RCR; /* Bankx Read Wait State Control Register */
		249	vu32 WCR; /* Bankx Write Wait State Control Register */
		250	vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
		251	vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
		252	vu32 BCR; /* Bankx Control Register */
196	killagreg	253	vu32 EMPTY1;
		254	vu32 BRDCR; /Bank x burst read wait delay register (EMI_BRDCRx) /
		255	} EMI_Bank_TypeDef;
1	ingob	256
		257	/---------------------------- Ethernet Controller ---------------------------/
		258
		259	/* MAC Registers */
		260	typedef struct
		261	{
		262	vu32 MCR; /* ENET Control Register */
		263	vu32 MAH; /* ENET Address High Register */
		264	vu32 MAL; /* ENET Address Low Register */
		265	vu32 MCHA; /* Multicast Address High Register */
		266	vu32 MCLA; /* Multicast Address Low Register */
		267	vu32 MIIA; /* MII Address Register */
		268	vu32 MIID; /* MII Data Register */
		269	vu32 MCF; /* ENET Control Frame Register */
		270	vu32 VL1; /* VLAN1 Register */
		271	vu32 VL2; /* VLAN2 register */
		272	vu32 MTS; /* ENET Transmission Status Register */
		273	vu32 MRS; /* ENET Reception Status Register */
		274	} ENET_MAC_TypeDef;
		275
		276	/* DMA Registers */
		277	typedef struct
		278	{
		279	vu32 SCR; /* DMA Status and Control Register */
		280	vu32 IER; /* DMA Interrupt Sources Enable Register */
		281	vu32 ISR; /* DMA Interrupt Status Register */
		282	vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
		283	ENET_CLK phase relations */
		284	vu32 RXSTR; /* Rx DMA start Register */
		285	vu32 RXCR; /* Rx DMA Control Register */
		286	vu32 RXSAR; /* Rx DMA Base Address Register */
		287	vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
		288	vu32 RXCAR; /* Rx DMA Current Address Register */
		289	vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
		290	vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
		291	vu32 RXSR; /* Rx DMA FIFO Status Register */
		292	vu32 TXSTR; /* Tx DMA start Register */
		293	vu32 TXCR; /* Tx DMA Control Register */
		294	vu32 TXSAR; /* Tx DMA Base Address Register */
		295	vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
		296	vu32 TXCAR; /* Tx DMA Current Address Register */
		297	vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
		298	vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
		299	vu32 TXSR; /* Tx DMA FIFO Status Register */
		300	} ENET_DMA_TypeDef;
		301
		302	/------------------------------------- GPIO ---------------------------------/
		303
		304	typedef struct
		305	{
		306	vu8 DR[1021]; /* Data Register */
		307	vu32 DDR; /* Data Direction Register */
		308	} GPIO_TypeDef;
		309
		310	/-------------------------------- I2C interface -----------------------------/
		311
		312	typedef struct
		313	{
		314	vu8 CR; /* Control Register */
		315	vu8 EMPTY1[3];
		316	vu8 SR1; /* Status Register 1 */
		317	vu8 EMPTY2[3];
		318	vu8 SR2; /* Status Register 2 */
		319	vu8 EMPTY3[3];
		320	vu8 CCR; /* Clock Control Register */
		321	vu8 EMPTY4[3];
		322	vu8 OAR1; /* Own Address Register 1 */
		323	vu8 EMPTY5[3];
		324	vu8 OAR2; /* Own Address Register 2 */
		325	vu8 EMPTY6[3];
		326	vu8 DR; /* Data Register */
		327	vu8 EMPTY7[3];
		328	vu8 ECCR; /* Extended Clock Control Register */
		329	vu8 EMPTY8[3];
		330	} I2C_TypeDef;
		331
		332	/------------------------------------- VIC ----------------------------------/
		333
		334	typedef struct
		335	{
		336	vu32 ISR; /* IRQ Status Register */
		337	vu32 FSR; /* FIQ Status Register */
		338	vu32 RINTSR; /* Raw Interrupt Status Register */
		339	vu32 INTSR; /* Interrupt Select Register */
		340	vu32 INTER; /* Interrupt Enable Register */
		341	vu32 INTECR; /* Interrupt Enable Clear Register */
		342	vu32 SWINTR; /* Software Interrupt Register */
		343	vu32 SWINTCR; /* Software Interrupt clear Register */
		344	vu32 PER; /* Protection Enable Register */
		345	vu32 EMPTY1[3];
		346	vu32 VAR; /* Vector Address Register */
		347	vu32 DVAR; /* Default Vector Address Register */
		348	vu32 EMPTY2[50];
		349	vu32 VAiR[16]; /* Vector Address 0-15 Register */
		350	vu32 EMPTY3[48];
		351	vu32 VCiR[16]; /* Vector Control 0-15 Register */
		352	} VIC_TypeDef;
		353
		354	/-------------------------------- Motor Control -----------------------------/
		355
		356	typedef struct
		357	{
		358	vu16 TCPT; /* Tacho Capture Register */
		359	vu16 EMPTY1;
		360	vu16 TCMP; /* Tacho Compare Register */
		361	vu16 EMPTY2;
		362	vu16 IPR; /* Input Pending Register */
		363	vu16 EMPTY3;
		364	vu16 TPRS; /* Tacho Prescaler Register */
		365	vu16 EMPTY4;
		366	vu16 CPRS; /* PWM Counter Prescaler Register */
		367	vu16 EMPTY5;
		368	vu16 REP; /* Repetition Counter Register */
		369	vu16 EMPTY6;
		370	vu16 CMPW; /* Compare Phase W Preload Register */
		371	vu16 EMPTY7;
		372	vu16 CMPV; /* Compare Phase V Preload Register */
		373	vu16 EMPTY8;
		374	vu16 CMPU; /* Compare Phase U Preload Register */
		375	vu16 EMPTY9;
		376	vu16 CMP0; /* Compare 0 Preload Register */
		377	vu16 EMPTY10;
		378	vu16 PCR0; /* Peripheral Control Register 0 */
		379	vu16 EMPTY11;
		380	vu16 PCR1; /* Peripheral Control Register 1 */
		381	vu16 EMPTY12;
		382	vu16 PCR2; /* Peripheral Control Register 2 */
		383	vu16 EMPTY13;
		384	vu16 PSR; /* Polarity Selection Register */
		385	vu16 EMPTY14;
		386	vu16 OPR; /* Output Peripheral Register */
		387	vu16 EMPTY15;
		388	vu16 IMR; /* Interrupt Mask Register */
		389	vu16 EMPTY16;
		390	vu16 DTG; /* Dead Time Generator Register */
		391	vu16 EMPTY17;
		392	vu16 ESC; /* Emergency Stop Clear Register */
		393	vu16 EMPTY18;
196	killagreg	394	vu16 ECR; /* Enhanced Control Register */
		395	vu16 EMPTY19;
		396	vu16 LOK; /* Lock Register */
		397	vu16 EMPTY20;
1	ingob	398	}MC_TypeDef;
		399
		400	/------------------------------------- RTC ----------------------------------/
		401
		402	typedef struct
		403	{
		404	vu32 TR; /* Time Register */
		405	vu32 DTR; /* Date Register */
		406	vu32 ATR; /* Alarm time Register */
		407	vu32 CR; /* Control Register */
		408	vu32 SR; /* Status Register */
		409	vu32 MILR; /* Millisec Register */
		410	}RTC_TypeDef;
		411
		412	/------------------------------------- SSP ----------------------------------/
		413
		414	typedef struct
		415	{
		416	vu16 CR0; /* Control Register 1 */
		417	vu16 EMPTY1;
		418	vu16 CR1; /* Control Register 2 */
		419	vu16 EMPTY2;
		420	vu16 DR; /* Data Register */
		421	vu16 EMPTY3;
		422	vu16 SR; /* Status Register */
		423	vu16 EMPTY4;
		424	vu16 PR; /* Clock Prescale Register */
		425	vu16 EMPTY5;
		426	vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
		427	vu16 EMPTY6;
		428	vu16 RISR; /* Raw Interrupt Status Register */
		429	vu16 EMPTY7;
		430	vu16 MISR; /* Masked Interrupt Status Register */
		431	vu16 EMPTY8;
		432	vu16 ICR; /* Interrupt Clear Register */
		433	vu16 EMPTY9;
		434	vu16 DMACR; /* DMA Control Register */
		435	vu16 EMPTY10;
		436	}SSP_TypeDef;
		437
		438	/------------------------------------ UART ----------------------------------/
		439
		440	typedef struct
		441	{
		442	vu16 DR; /* Data Register */
		443	vu16 EMPTY1;
		444	vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
		445	vu16 EMPTY2[9];
		446	vu16 FR; /* Flag Register */
		447	vu16 EMPTY3[3];
		448	vu16 ILPR; /* IrDA Low-Power counter Register */
		449	vu16 EMPTY4;
		450	vu16 IBRD; /* Integer Baud Rate Divisor Register */
		451	vu16 EMPTY5;
		452	vu16 FBRD; /* Fractional Baud Rate Divisor Register */
		453	vu16 EMPTY6;
		454	vu16 LCR; /* Line Control Register, High byte */
		455	vu16 EMPTY7;
		456	vu16 CR; /* Control Register */
		457	vu16 EMPTY8;
		458	vu16 IFLS; /* Interrupt FIFO Level Select Register */
		459	vu16 EMPTY9;
		460	vu16 IMSC; /* Interrupt Mask Set/Clear Register */
		461	vu16 EMPTY10;
		462	vu16 RIS; /* Raw Interrupt Status Register */
		463	vu16 EMPTY11;
		464	vu16 MIS; /* Masked Interrupt Status Register */
		465	vu16 EMPTY12;
		466	vu16 ICR; /* Interrupt Clear Register */
		467	vu16 EMPTY13;
		468	vu16 DMACR; /* DMA Control Register */
		469	vu16 EMPTY14;
		470	}UART_TypeDef;
		471
		472	/------------------------------- Wake-up System -----------------------------/
		473
		474	typedef struct
		475	{
		476	vu32 CTRL; /* Control Register */
		477	vu32 MR; /* Mask Register */
		478	vu32 TR; /* Trigger Register */
		479	vu32 PR; /* Pending Register */
		480	vu32 INTR; /* Software Interrupt Register */
		481	} WIU_TypeDef;
		482
		483	/------------------------------- WatchDog Timer -----------------------------/
		484
		485	typedef struct
		486	{
		487	vu16 CR; /* Control Register */
		488	vu16 EMPTY1;
		489	vu16 PR; /* Presclar Register */
		490	vu16 EMPTY2;
		491	vu16 VR; /* Pre-load Value Register */
		492	vu16 EMPTY3;
		493	vu16 CNT; /* Counter Register */
		494	vu16 EMPTY4;
		495	vu16 SR; /* Status Register */
		496	vu16 EMPTY5;
		497	vu16 MR; /* Mask Register */
		498	vu16 EMPTY6;
		499	vu16 KR; /* Key Register */
		500	vu16 EMPTY7;
		501	} WDG_TypeDef;
		502
		503	/*******************************************************************************
		504	* Memory Mapping of STR91x *
		505	*******************************************************************************/
		506
		507	#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
		508	#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
		509
		510	#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
		511	#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
		512
		513	#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
		514	#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
		515
		516	#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
		517	#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
		518
		519	#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
		520	#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
		521
		522	#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
		523	#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
		524
		525	#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
		526	#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
		527
		528	#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
		529	#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
		530
		531	/*******************************************************************************
		532	* Addresses related to the VICs' peripherals *
		533	*******************************************************************************/
		534
		535	#define VIC0_BASE (AHB_VIC0_U)
		536	#define VIC1_BASE (AHB_VIC1_U)
		537
		538	/*******************************************************************************
		539	* Addresses related to the EMI banks *
		540	*******************************************************************************/
		541
		542	#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
		543	#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
		544	#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
		545	#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
196	killagreg	546	#define AHB_EMICCR_OFST (0x00000204) /* Offset of EMI_CCR Register */
1	ingob	547
		548	/*******************************************************************************
		549	* Addresses related to the DMA peripheral *
		550	*******************************************************************************/
		551
		552	#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
		553	#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
		554	#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
		555	#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
		556	#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
		557	#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
		558	#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
		559	#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
		560
		561	/*******************************************************************************
		562	* Addresses related to the APB0 sub-system *
		563	*******************************************************************************/
		564
		565	#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
		566	#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
		567	#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
		568	#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
		569	#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
		570	#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
		571	#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
		572	#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
		573	#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
		574	#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
		575	#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
		576	#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
		577	#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
		578	#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
		579	#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
		580
		581	/*******************************************************************************
		582	* Addresses related to the APB1 sub-system *
		583	*******************************************************************************/
		584
		585	#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
		586	#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
		587	#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
		588	#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
		589	#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
		590	#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
		591	#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
		592	#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
		593	#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
		594	#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
		595	#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */
		596	#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */
		597	#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */
		598
		599	/----------------------------------------------------------------------------/
		600	/----------------------------- Unbuffered Mode ------------------------------/
		601	/----------------------------------------------------------------------------/
		602
196	killagreg	603	#ifndef Buffered
1	ingob	604
		605	/*******************************************************************************
		606	* AHBAPB peripheral Unbuffered Base Address *
		607	*******************************************************************************/
		608
		609	#define AHBAPB0_BASE (AHB_APB_BRDG0_U)
		610	#define AHBAPB1_BASE (AHB_APB_BRDG1_U)
		611
		612	/*******************************************************************************
		613	* ENET peripheral Unbuffered Base Address *
		614	*******************************************************************************/
		615
		616	#define ENET_MAC_BASE (AHB_ENET_MAC_U)
		617	#define ENET_DMA_BASE (AHB_ENET_DMA_U)
		618
		619	/*******************************************************************************
		620	* DMA peripheral Unbuffered Base Address *
		621	*******************************************************************************/
		622
		623	#define DMA_BASE (AHB_DMA_U)
		624
		625	/*******************************************************************************
		626	* EMI peripheral Unbuffered Base Address *
		627	*******************************************************************************/
		628
		629	#define EMI_BASE (AHB_EMI_U)
		630
		631	/*******************************************************************************
		632	* FMI peripheral Unbuffered Base Address *
		633	*******************************************************************************/
		634
		635	#define FMI_BASE (AHB_FMI_U)
		636
		637
196	killagreg	638	#else /* Buffered */
1	ingob	639
		640	/----------------------------------------------------------------------------/
		641	/------------------------------ Buffered Mode -------------------------------/
		642	/----------------------------------------------------------------------------/
		643
		644	/*******************************************************************************
		645	* AHBAPB peripheral Buffered Base Address *
		646	*******************************************************************************/
		647
		648	#define AHBAPB0_BASE (AHB_APB_BRDG0_B)
		649	#define AHBAPB1_BASE (AHB_APB_BRDG1_B)
		650
		651	/*******************************************************************************
		652	* ENET peripheral Unbuffered Base Address *
		653	*******************************************************************************/
		654
		655	#define ENET_MAC_BASE (AHB_ENET_MAC_B)
		656	#define ENET_DMA_BASE (AHB_ENET_DMA_B)
		657
		658	/*******************************************************************************
		659	* DMA peripheral Buffered Base Address *
		660	*******************************************************************************/
		661
		662	#define DMA_BASE (AHB_DMA_B)
		663
		664	/*******************************************************************************
		665	* EMI peripheral Buffered Base Address *
		666	*******************************************************************************/
		667
		668	#define EMI_BASE (AHB_EMI_B)
		669
		670	/*******************************************************************************
		671	* FMI peripheral Buffered Base Address *
		672	*******************************************************************************/
		673
		674	#define FMI_BASE (AHB_FMI_B)
		675
196	killagreg	676	#endif /* Buffered */
1	ingob	677
		678	/*******************************************************************************
		679	* DMA channels Base Address *
		680	*******************************************************************************/
		681	#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST)
		682	#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST)
		683	#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST)
		684	#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST)
		685	#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST)
		686	#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST)
		687	#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST)
		688	#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST)
		689
		690	/*******************************************************************************
		691	* EMI Banks peripheral Base Address *
		692	*******************************************************************************/
		693
		694	#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST)
		695	#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST)
		696	#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST)
		697	#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST)
196	killagreg	698	#define EMI_CCR_BASE (EMI_BASE + AHB_EMICCR_OFST)
1	ingob	699
		700	/*******************************************************************************
		701	* APB0 Peripherals' Base addresses *
		702	*******************************************************************************/
		703
		704	#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST)
		705	#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST)
		706	#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST)
		707	#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST)
		708	#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST)
		709	#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST)
		710	#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST)
		711	#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST)
		712	#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST)
		713	#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST)
		714	#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST)
		715	#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST)
		716	#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST)
		717	#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST)
		718	#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST)
		719
		720	/*******************************************************************************
		721	* APB1 Peripherals' Base addresses *
		722	*******************************************************************************/
		723
		724	#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST)
		725	#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST)
		726	#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST)
		727	#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST)
		728	#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST)
		729	#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST)
		730	#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST)
		731	#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST)
		732	#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST)
		733	#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST)
		734	#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST)
		735	#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST)
		736	#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST)
		737
		738	/*******************************************************************************
		739	* IPs' declaration *
		740	*******************************************************************************/
		741
		742	/------------------------------ Non Debug Mode ------------------------------/
		743
196	killagreg	744	#ifndef DEBUG
1	ingob	745
		746	/********************************* AHBAPB *********************************/
		747
		748	#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE)
		749	#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE)
		750
		751	/*********************************** EMI **********************************/
		752
		753	#define EMI ((EMI_TypeDef *)EMI_BASE)
		754
		755	/*********************************** DMA **********************************/
		756
		757	#define DMA ((DMA_TypeDef *)DMA_BASE)
		758	#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
		759	#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
		760	#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
		761	#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
		762	#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
		763	#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
		764	#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
		765	#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
		766
		767	/*********************************** EMI **********************************/
		768
		769	#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
		770	#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
		771	#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
		772	#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
196	killagreg	773	#define EMI_CCR (vu32*)EMI_CCR_BASE
1	ingob	774	/*********************************** ENET_MAC **********************************/
		775
		776	#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
		777
		778	/*********************************** ENET_DMA **********************************/
		779
		780	#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
		781
		782	/*********************************** FMI **********************************/
		783
		784	#define FMI ((FMI_TypeDef *)FMI_BASE)
		785
		786	/*********************************** VIC **********************************/
		787
		788	#define VIC0 ((VIC_TypeDef *)VIC0_BASE)
		789	#define VIC1 ((VIC_TypeDef *)VIC1_BASE)
		790
		791	/*******************************************************************************
		792	* APB0 Peripherals' *
		793	*******************************************************************************/
		794	#define WIU ((WIU_TypeDef *)WIU_BASE)
		795	#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
		796	#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
		797	#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
		798	#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
		799	#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
		800	#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
		801	#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
		802	#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE)
		803	#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE)
		804	#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE)
		805	#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE)
		806	#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE)
		807	#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE)
		808	#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE)
		809	/*******************************************************************************
		810	* APB1 Peripherals' *
		811	*******************************************************************************/
		812	#define RTC ((RTC_TypeDef *)RTC_BASE)
		813	#define SCU ((SCU_TypeDef *)SCU_BASE)
		814	#define MC ((MC_TypeDef *)MC_BASE)
		815	#define UART0 ((UART_TypeDef *)UART0_BASE)
		816	#define UART1 ((UART_TypeDef *)UART1_BASE)
		817	#define UART2 ((UART_TypeDef *)UART2_BASE)
		818	#define SSP0 ((SSP_TypeDef *)SSP0_BASE)
		819	#define SSP1 ((SSP_TypeDef *)SSP1_BASE)
		820	#define CAN ((CAN_TypeDef *)CAN_BASE)
		821	#define ADC ((ADC_TypeDef *)ADC_BASE)
		822	#define WDG ((WDG_TypeDef *)WDG_BASE)
		823	#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
		824	#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
		825	#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
		826	#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
		827
196	killagreg	828	#else /* DEBUG */
1	ingob	829
		830	/-------------------------------- Debug Mode --------------------------------/
		831
		832	#ifdef _AHBAPB0
		833	EXT AHBAPB_TypeDef *AHBAPB0;
		834	#endif /* _AHBAPB0 */
		835
		836	#ifdef _AHBAPB1
		837	EXT AHBAPB_TypeDef *AHBAPB1;
		838	#endif /_AHBAPB1 /
		839
		840
		841	#ifdef _DMA
		842	EXT DMA_TypeDef *DMA;
		843	#endif /* _DMA */
		844
196	killagreg	845
1	ingob	846	#ifdef _DMA_Channel0
		847	EXT DMA_Channel_TypeDef *DMA_Channel0;
		848	#endif /* _DMA_Channel0 */
		849
		850	#ifdef _DMA_Channel1
		851	EXT DMA_Channel_TypeDef *DMA_Channel1;
		852	#endif /* _DMA_Channel1 */
		853
		854	#ifdef _DMA_Channel2
		855	EXT DMA_Channel_TypeDef *DMA_Channel2;
		856	#endif /* _DMA_Channel0 */
		857
		858	#ifdef _DMA_Channel3
		859	EXT DMA_Channel_TypeDef *DMA_Channel3;
		860	#endif /* _DMA_Channel0 */
		861
		862	#ifdef _DMA_Channel4
		863	EXT DMA_Channel_TypeDef *DMA_Channel4;
		864	#endif /* _DMA_Channel4 */
		865
		866	#ifdef _DMA_Channel5
		867	EXT DMA_Channel_TypeDef *DMA_Channel5;
		868	#endif /* _DMA_Channel5 */
		869
		870	#ifdef _DMA_Channel6
		871	EXT DMA_Channel_TypeDef *DMA_Channel6;
		872	#endif /* _DMA_Channel6 */
		873
		874	#ifdef _DMA_Channel7
		875	EXT DMA_Channel_TypeDef *DMA_Channel7;
		876	#endif /* _DMA_Channel7 */
		877
196	killagreg	878	#ifdef _EMI
		879	EXT vu32 *EMI_CCR;
		880	#endif /_EMI /
		881
		882
1	ingob	883	#ifdef _EMI_Bank0
		884	EXT EMI_Bank_TypeDef *EMI_Bank0;
		885	#endif /* _EMI_Bank0 */
		886
		887	#ifdef _EMI_Bank1
		888	EXT EMI_Bank_TypeDef *EMI_Bank1;
		889	#endif /* _EMI_Bank1 */
		890
		891	#ifdef _EMI_Bank2
		892	EXT EMI_Bank_TypeDef *EMI_Bank2;
		893	#endif /* _EMI_Bank2 */
		894
		895	#ifdef _EMI_Bank3
		896	EXT EMI_Bank_TypeDef *EMI_Bank3;
		897	#endif /* _EMI_Bank3 */
		898
		899	#ifdef _FMI
		900	EXT FMI_TypeDef *FMI;
		901	#endif /* _FMI */
		902
		903	#ifdef _VIC0
		904	EXT VIC_TypeDef *VIC0;
		905	#endif /* _VIC0 */
		906
		907	#ifdef _VIC1
		908	EXT VIC_TypeDef *VIC1;
		909	#endif /* _VIC1 */
		910
		911	#ifdef _WIU
		912	EXT WIU_TypeDef *WIU;
		913	#endif /* _WIU */
		914
		915	#ifdef _TIM0
		916	EXT TIM_TypeDef *TIM0;
		917	#endif /* _TIM0 */
		918
		919	#ifdef _TIM1
		920	EXT TIM_TypeDef *TIM1;
		921	#endif /* _TIM1 */
		922
		923	#ifdef _TIM2
		924	EXT TIM_TypeDef *TIM2;
		925	#endif /* _TIM2 */
		926
		927	#ifdef _TIM3
		928	EXT TIM_TypeDef *TIM3;
		929	#endif /* _TIM3 */
		930
		931	#ifdef _GPIO0
		932	EXT GPIO_TypeDef *GPIO0;
		933	#endif /* _GPIO0 */
		934
		935	#ifdef _GPIO1
		936	EXT GPIO_TypeDef *GPIO1;
		937	#endif /* _GPIO1 */
		938
		939	#ifdef _GPIO2
		940	EXT GPIO_TypeDef *GPIO2;
		941	#endif /* _GPIO2 */
		942
		943	#ifdef _GPIO3
		944	EXT GPIO_TypeDef *GPIO3;
		945	#endif /* _GPIO3 */
		946
		947
		948	#ifdef _GPIO4
		949	EXT GPIO_TypeDef *GPIO4;
		950	#endif /* _GPIO4 */
		951
		952	#ifdef _GPIO5
		953	EXT GPIO_TypeDef *GPIO5;
		954	#endif /* _GPIO5 */
		955
		956	#ifdef _GPIO6
		957	EXT GPIO_TypeDef *GPIO6;
		958	#endif /* _GPIO6 */
		959
		960
		961	#ifdef _GPIO7
		962	EXT GPIO_TypeDef *GPIO7;
		963	#endif /* _GPIO7 */
		964
		965	#ifdef _GPIO8
		966	EXT GPIO_TypeDef *GPIO8;
		967	#endif /* _GPIO8 */
		968
		969	#ifdef _GPIO9
		970	EXT GPIO_TypeDef *GPIO9;
		971	#endif /* _GPIO9 */
		972
		973	#ifdef _RTC
		974	EXT RTC_TypeDef *RTC;
		975	#endif /* _RTC */
		976
		977
		978	#ifdef _SCU
		979	EXT SCU_TypeDef *SCU;
		980	# endif /* _SCU */
		981
		982	#ifdef _MC
		983	EXT MC_TypeDef *MC;
		984	#endif /* _MC */
		985
		986	#ifdef _UART0
		987	EXT UART_TypeDef *UART0;
		988	#endif /* _UART0 */
		989
		990	#ifdef _UART1
		991	EXT UART_TypeDef *UART1;
		992	#endif /* _UART1 */
		993
		994	#ifdef _UART2
		995	EXT UART_TypeDef *UART2;
		996	#endif /* _UART2*/
		997
		998	#ifdef _SSP0
		999	EXT SSP_TypeDef *SSP0;
		1000	#endif /* _SSP0 */
		1001
		1002	#ifdef _SSP1
		1003	EXT SSP_TypeDef *SSP1;
		1004	#endif /* _SSP1 */
		1005
		1006	#ifdef _CAN
		1007	EXT CAN_TypeDef *CAN;
		1008	#endif /* _CAN */
		1009
		1010	#ifdef _ADC
		1011	EXT ADC_TypeDef *ADC;
		1012	#endif /* _ADC */
		1013
		1014	#ifdef _WDG
		1015	EXT WDG_TypeDef *WDG;
		1016	#endif /* _WDG */
		1017
		1018	#ifdef _I2C0
		1019	EXT I2C_TypeDef *I2C0;
		1020	#endif /* _I2C0 */
		1021
		1022	#ifdef _I2C1
		1023	EXT I2C_TypeDef *I2C1;
		1024	#endif /* _I2C1 */
		1025
		1026	#ifdef _ENET
		1027	EXT ENET_MAC_TypeDef *ENET_MAC;
		1028	EXT ENET_DMA_TypeDef *ENET_DMA;
		1029	#endif /* _ENET */
		1030
196	killagreg	1031	#endif /* DEBUG */
		1032
1	ingob	1033	#endif /* __91x_MAP_H*/
		1034
196	killagreg	1035	/***************** (C) COPYRIGHT 2008 STMicroelectronics *END OF FILE**/
1	ingob	1036

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(root)/tags/V2.10e/libstr91x/include/91x_map.h - Rev 653