Subversion Repositories FlightCtrl

Rev

Rev 1868 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
1612 dongfang 1
#include <avr/io.h>
2
#include <avr/interrupt.h>
3
#include "uart1.h"
2039 - 4
#include "ubx.h"
1612 dongfang 5
 
6
#define USART1_BAUD 57600
7
 
8
/****************************************************************/
9
/*              Initialization of the USART1                    */
10
/****************************************************************/
2039 - 11
void usart1_init(void) {
1612 dongfang 12
        // USART1 Control and Status Register A, B, C and baud rate register
13
        uint8_t sreg = SREG;
2039 - 14
        uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU / (8 * USART1_BAUD) - 1);
1612 dongfang 15
 
16
        // disable all interrupts before reconfiguration
17
        cli();
18
 
2039 - 19
        // disable RX-Interrupt, disable TX-Interrupt, disable DRE-Interrupt
20
        UCSR1B &= ~ ((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1));
1612 dongfang 21
 
22
        // set direction of RXD1 and TXD1 pins
2039 - 23
        // set RXD1 (PD2) as an input pin,  set TXD1 (PD3) as an output pin
24
        PORTD |= (1 << PORTD2) | (1 << PORTD3);
1612 dongfang 25
        DDRD &= ~(1 << DDD2);
1821 - 26
        DDRD |= (1 << DDD3);
1612 dongfang 27
 
28
        // USART0 Baud Rate Register
29
        // set clock divider
1821 - 30
        UBRR1H = (uint8_t) (ubrr >> 8);
31
        UBRR1L = (uint8_t) ubrr;
1612 dongfang 32
 
33
        // enable double speed operation
34
        UCSR1A |= (1 << U2X1);
35
        // enable receiver and transmitter
36
        UCSR1B = (1 << TXEN1) | (1 << RXEN1);
2039 - 37
        // set asynchronous mode,  no parity, 1 stop bit
38
        UCSR1C &= ~((1 << UMSEL11) | (1 << UMSEL10) | (1 << UPM11) | (1 << UPM10) | (1 << USBS1));
39
 
1612 dongfang 40
        // 8-bit
41
        UCSR1B &= ~(1 << UCSZ12);
2039 - 42
        UCSR1C |= (1 << UCSZ11) | (1 << UCSZ10);
1612 dongfang 43
 
44
        // flush receive buffer explicit
1821 - 45
        while (UCSR1A & (1 << RXC1))
46
                UDR1;
1612 dongfang 47
 
48
        // enable interrupts at the end
49
        // enable RX-Interrupt
50
        UCSR1B |= (1 << RXCIE1);
51
        // enable TX-Interrupt
52
        //UCSR1B |= (1 << TXCIE1);
53
        // enable DRE interrupt
54
        //UCSR1B |= (1 << UDRIE1);
55
 
56
        // restore global interrupt flags
1821 - 57
        SREG = sreg;
1612 dongfang 58
}
59
 
60
/****************************************************************/
61
/*               USART1 data register empty ISR                 */
62
/****************************************************************/
1645 - 63
/*ISR(USART1_UDRE_vect) {
1821 - 64
 }
65
 */
1612 dongfang 66
 
67
/****************************************************************/
68
/*               USART1 transmitter ISR                         */
69
/****************************************************************/
1645 - 70
/*ISR(USART1_TX_vect) {
1821 - 71
 }
72
 */
1612 dongfang 73
/****************************************************************/
74
/*               USART1 receiver ISR                            */
75
/****************************************************************/
2039 - 76
ISR(USART1_RX_vect) {
77
    ubx_parser(UDR1);  // get data byte and put it into the ubx protocol parser
1612 dongfang 78
}