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Rev | Author | Line No. | Line |
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1 | ingob | 1 | /*############################################################################ |
2 | ############################################################################*/ |
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3 | |||
4 | #ifndef BLMC_H_ |
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5 | #define BLMC_H_ |
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6 | |||
7 | extern volatile unsigned char Phase; |
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8 | extern volatile unsigned char ShadowTCCR1A; |
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9 | extern volatile unsigned char CompInterruptFreigabe; |
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10 | |||
11 | void Blc(void); |
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12 | void Manuell(void); |
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13 | |||
14 | #ifdef _32KHZ |
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31 | Nick666 | 15 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x49; DDRB = 0x0A;} |
16 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x49; DDRB = 0x0C;} |
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17 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x69; DDRB = 0x08;} |
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18 | #define PWM_OFF {TCCR1A = 0x01; TCCR2 = 0x49; PORTC &= ~0x0E;} |
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1 | ingob | 19 | #endif |
20 | |||
21 | #ifdef _16KHZ |
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31 | Nick666 | 22 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x41; DDRB = 0x0A;} |
23 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x41; DDRB = 0x0C;} |
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24 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x08;} |
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25 | #define PWM_OFF {TCCR1A = 0x01; TCCR2 = 0x41; PORTC &= ~0x0E;} |
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1 | ingob | 26 | #endif |
27 | |||
28 | |||
29 | #define STEUER_A_H {PWM_A_ON} |
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30 | #define STEUER_B_H {PWM_B_ON} |
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31 | #define STEUER_C_H {PWM_C_ON} |
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32 | |||
33 | #define STEUER_A_L {PORTD &= ~0x30; PORTD |= 0x08;} |
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34 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
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35 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
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36 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF;} |
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37 | |||
38 | #define SENSE_A ADMUX = 0; |
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39 | #define SENSE_B ADMUX = 1; |
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40 | #define SENSE_C ADMUX = 2; |
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41 | |||
42 | #define ClrSENSE ACSR |= 0x10 |
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43 | #define SENSE ((ACSR & 0x10)) |
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44 | #define SENSE_L (!(ACSR & 0x20)) |
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45 | #define SENSE_H ((ACSR & 0x20)) |
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46 | #define ENABLE_SENSE_INT {CompInterruptFreigabe = 1;ACSR |= 0x0A; } |
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47 | #define DISABLE_SENSE_INT {CompInterruptFreigabe = 0; ACSR &= ~0x08; } |
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48 | |||
49 | |||
50 | #define SENSE_FALLING_INT ACSR &= ~0x01 |
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51 | #define SENSE_RISING_INT ACSR |= 0x03 |
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52 | #define SENSE_TOGGLE_INT ACSR &= ~0x03 |
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53 | |||
54 | #endif //BLMC_H_ |
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55 |