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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 687 | killagreg | 1 | #include <avr/io.h> |
| 2 | #include <avr/interrupt.h> |
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| 3 | |||
| 4 | |||
| 684 | killagreg | 5 | #include "main.h" |
| 6 | #include "uart1.h" |
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| 7 | #include "fifo.h" |
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| 8 | #include "ubx.h" |
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| 9 | |||
| 10 | |||
| 11 | |||
| 12 | // FIFO-objects and buffers for input and output |
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| 13 | |||
| 14 | //#define BUFSIZE_IN 0x96 |
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| 15 | //volatile uint8_t inbuf[BUFSIZE_IN]; |
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| 16 | //fifo_t infifo; |
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| 17 | |||
| 18 | #define BUFSIZE_OUT 0x96 |
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| 19 | volatile uint8_t outbuf[BUFSIZE_OUT]; |
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| 20 | fifo_t outfifo; |
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| 21 | |||
| 22 | /****************************************************************/ |
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| 23 | /* Initialization of the USART1 */ |
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| 24 | /****************************************************************/ |
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| 25 | void USART1_Init (void) |
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| 26 | { |
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| 27 | // USART1 Control and Status Register A, B, C and baud rate register |
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| 28 | uint8_t sreg = SREG; |
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| 29 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
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| 30 | |||
| 31 | // disable all interrupts before reconfiguration |
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| 32 | cli(); |
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| 33 | |||
| 34 | // disable RX-Interrupt |
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| 35 | UCSR1B &= ~(1 << RXCIE1); |
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| 36 | // disable TX-Interrupt |
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| 37 | UCSR1B &= ~(1 << TXCIE1); |
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| 38 | // disable DRE-Interrupt |
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| 39 | UCSR1B |= (1 << UDRIE1); |
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| 40 | |||
| 41 | // disable receiver and transmitter (will flush the buffers) |
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| 42 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
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| 43 | |||
| 44 | // set direction of RXD1 and TXD1 pins |
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| 45 | // set RXD1 (PD2) as an input pin |
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| 701 | killagreg | 46 | DDRD &= ~(1 << DDD2); |
| 684 | killagreg | 47 | PORTD |= (1 << PORTD2); |
| 701 | killagreg | 48 | |
| 684 | killagreg | 49 | // set TXD1 (PD3) as an output pin |
| 701 | killagreg | 50 | DDRD |= (1 << DDD3); |
| 684 | killagreg | 51 | PORTD |= (1 << PORTD3); |
| 52 | |||
| 53 | // USART0 Baud Rate Register |
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| 54 | // set clock divider |
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| 55 | UBRR1H = (uint8_t)(ubrr>>8); |
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| 56 | UBRR1L = (uint8_t)ubrr; |
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| 57 | |||
| 58 | // enable double speed operation |
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| 59 | UCSR1A |= (1 << U2X1); |
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| 60 | // enable receiver and transmitter |
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| 61 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
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| 62 | // set asynchronous mode |
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| 63 | UCSR1C &= ~(1 << UMSEL11); |
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| 64 | UCSR1C &= ~(1 << UMSEL10); |
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| 65 | // no parity |
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| 66 | UCSR1C &= ~(1 << UPM11); |
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| 67 | UCSR1C &= ~(1 << UPM10); |
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| 68 | // 1 stop bit |
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| 69 | UCSR1C &= ~(1 << USBS1); |
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| 70 | // 8-bit |
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| 71 | UCSR1B &= ~(1 << UCSZ12); |
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| 72 | UCSR1C |= (1 << UCSZ11); |
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| 73 | UCSR1C |= (1 << UCSZ10); |
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| 74 | |||
| 75 | // flush receive buffer explicit |
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| 76 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
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| 77 | |||
| 78 | // enable interrupts at the end |
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| 79 | // enable RX-Interrupt |
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| 80 | UCSR1B |= (1 << RXCIE1); |
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| 81 | // enable TX-Interrupt |
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| 82 | //UCSR1B |= (1 << TXCIE1); |
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| 83 | // enable DRE interrupt |
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| 84 | //UCSR1B |= (1 << UDRIE1); |
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| 85 | |||
| 86 | |||
| 87 | // restore global interrupt flags |
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| 88 | SREG = sreg; |
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| 89 | |||
| 90 | // inint FIFO buffer |
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| 91 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
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| 92 | fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
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| 93 | } |
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| 94 | |||
| 95 | int16_t USART1_putc (const uint8_t c) |
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| 96 | { |
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| 97 | int16_t ret = fifo_put (&outfifo, c); |
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| 98 | // create an data register empty interrupt |
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| 99 | UCSR1B |= (1 << UDRIE1); |
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| 100 | |||
| 101 | return ret; |
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| 102 | } |
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| 103 | |||
| 104 | /*int16_t USART1_getc_nowait () |
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| 105 | { |
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| 106 | return fifo_get_nowait (&infifo); |
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| 107 | } |
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| 108 | |||
| 109 | |||
| 110 | uint8_t USART1_getc_wait () |
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| 111 | { |
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| 112 | return fifo_get_wait (&infifo); |
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| 113 | } |
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| 114 | */ |
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| 115 | |||
| 116 | /****************************************************************/ |
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| 117 | /* USART1 data register empty ISR */ |
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| 118 | /****************************************************************/ |
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| 119 | ISR(USART1_UDRE_vect) |
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| 120 | { |
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| 121 | // Move a character from the output buffer to the data register. |
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| 122 | // When the character was processed the next interrupt is generated. |
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| 123 | // If the output buffer is empty the DRE-interrupt is disabled. |
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| 124 | if (outfifo.count > 0) |
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| 125 | UDR1 = _inline_fifo_get (&outfifo); |
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| 126 | else |
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| 127 | UCSR1B &= ~(1 << UDRIE1); |
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| 128 | } |
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| 129 | |||
| 130 | /****************************************************************/ |
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| 131 | /* USART1 transmitter ISR */ |
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| 132 | /****************************************************************/ |
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| 133 | ISR(USART1_TX_vect) |
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| 134 | { |
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| 135 | |||
| 136 | } |
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| 137 | |||
| 138 | /****************************************************************/ |
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| 139 | /* USART1 receiver ISR */ |
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| 140 | /****************************************************************/ |
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| 141 | ISR(USART1_RX_vect) |
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| 142 | { |
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| 143 | uint8_t c; |
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| 144 | c = UDR0; // get data byte |
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| 145 | ubx_parser(c); // and put it into the ubx protocol parser |
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| 146 | } |